ASIC Packaging Signal/Power Integrity Hardware Engineer

Cisco

. Develop, document, and implement design rules for ultra-high-speed signaling .

Posted 10/1/2026full-timeSan Jose • California • United StatesMid-LevelSenior💰 $155,000 - $222,600 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in signal and power integrity analysis, high-speed design principles, and advanced packaging techniques. Proficient in using industry-standard EDA tools for design validation and simulation.

Highest-signal resume keywords

Signal Integrity AnalysisPower Integrity AnalysisHigh-Speed Design PrinciplesEDA Tool ProficiencyAdvanced Packaging Techniques

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Signal IntegrityPower IntegrityTransmission Line TheoryElectromagneticsImpedance Network Analysis56G PAM4 SerDes ArchitecturesPre- and Post-Layout SimulationsCircuit-Level AnalysisChannel ModelingBER Prediction

Soft Skills

Technical Communication

Tools & Technologies

Cadence SigrityAnsys HFSSKeysight ADSCadence APDAnsys EMSPICEVector Network AnalysisIBIS

Industry Keywords

High-Speed Memory InterfaceCoWoSEMIBInterposer-Based DesignsDie-to-Die Interfaces

About the role

Key responsibilities & impact

Develop, document, and implement design rules for ultra-high-speed signaling
Ensure power, performance, and area goals are met for products
Analyze substrate signal integrity and power integrity
Collaborate with layout teams to optimize solutions across interposer, substrate, and PCB
Design, document, and develop ASIC packages for high-volume, high-quality release
Perform post-layout extraction and reporting
Collaborate with system partners, vendors, and design leads
Achieve combined power and signal integrity
Resolve complex technical issues using advanced technology design rules

Requirements

What you’ll need

Bachelor’s degree in Electrical Engineering and 4+ years of relevant signal and power integrity experience, or Master’s degree in Electrical Engineering and 2+ years of relevant experience, or PhD in Electrical Engineering and 0+ years of related experience, or equivalent related work experience
Experience with high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis
Experience applying high-speed design principles to 56G PAM4 SerDes architectures, channel modeling, and BER prediction
Experience with pre- and post-layout SI/PI simulations
Proficiency with industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS
Experience conducting layout reviews and physical design validation using Cadence APD and Ansys EM flows
Experience with SPICE for circuit-level analysis, signal modeling, and performance validation
Preferred: ability to articulate technical concepts to diverse audiences
Preferred: experience with HBM or high-speed memory interface SI
Preferred: experience with UCIe or proprietary die-to-die interfaces
Preferred: experience with advanced packaging such as CoWoS, EMIB, and interposer-based designs
Preferred: experience with Vector Network Analysis
Preferred: experience with IBIS

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid birthday day off
Paid year-end holiday shutdown
4 paid personal wellness days
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1st
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses may be available for non-sales roles