ASIC Physical Design Engineer

Cisco

. Own and drive RTL-to-GDSII implementation for advanced nodes from sub-16nm to 2nm .

Posted 9/21/2026full-timeUnited StatesMid-LevelSenior💰 $167,700 - $245,200 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in RTL-to-GDSII implementation for advanced nodes, with a strong focus on hierarchical floorplanning, timing closure, and static timing analysis. Proficient in scripting and utilizing industry-standard tools for ASIC physical design and implementation.

Highest-signal resume keywords

RTL-To-GDSII ImplementationStatic Timing AnalysisHierarchical FloorplanningScripting With TCL And PythonPlace And Route Experience

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

ASIC Physical DesignTiming ClosurePower Integrity AnalysisHierarchical Design MethodologyClock And Power DistributionGlobal Signal PlanningTiming ECO StrategiesAutomated ScriptingMulti-Mode/Multi-Corner DesignsDesigns Over 100M Gates

Tools & Technologies

Cadence InnovusSynopsys FCCadence GenusSynopsys FormalityCadence LECPrimeTime-DMSAApache RedhawkVoltusSynopsys ICVMentor Calibre

Industry Keywords

Electrical EngineeringAdvanced NodesSub-16nm2nmDesign MethodologyTiming ConvergenceMethodology AlignmentQuality And Efficiency GapsDebugging SolutionsBest Practices

Tech Stack

Tools & technologies

ApachePython

About the role

Key responsibilities & impact

Own and drive RTL-to-GDSII implementation for advanced nodes from sub-16nm to 2nm
Define and execute hierarchical floorplanning, place and route, clock and power distribution, and timing convergence strategies
Perform static timing analysis, setup reviews, and sign-offs for multi-mode/multi-corner designs
Develop automated scripts within STA tools
Implement and manage timing ECO strategies using Prime Closure and PrimeTime
Analyze quality and efficiency gaps and recommend tool, flow, and methodology improvements
Collaborate with RTL, DFT, EDA vendors, and tool owners to improve design and implementation efficiency
Evaluate and implement new timing methodologies and provide creative debugging solutions
Contribute to best practices and drive methodology alignment across projects

Requirements

What you’ll need

Bachelor’s degree in Electrical Engineering plus 5 years of related experience, or Master’s degree in Electrical Engineering plus 2 years of related experience, or PhD in Electrical Engineering plus 0+ years of related experience
Hands-on experience in ASIC physical design and implementation
Experience with hierarchical floorplanning, clock and power distribution, global signal and I/O planning, physical convergence, timing closure, and hierarchical design methodology
Experience with power integrity analysis
Experience working on designs over 100M gates in advanced nodes including 16nm, 14nm, 7nm, 5nm, 3nm, or 2nm
Scripting experience with TCL, Python, and efficient use of AI tools
Place and route experience with Cadence Innovus or Synopsys FC
Synthesis experience with Cadence Genus or Synopsys FC
Formal verification experience with Synopsys Formality or Cadence LEC
Static timing analysis experience with tools such as PrimeTime-DMSA
Power integrity experience with Apache Redhawk or Voltus
Physical verification experience with Synopsys ICV or Mentor Calibre

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
Paid birthday day off
Paid year-end holiday shutdown
4 paid personal wellness days
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco policies