ASIC Physical Design Engineer

Cisco

. Perform RTL-to-GDSII implementation, including hierarchical floorplanning, place and route, static timing analysis, power integrity, and equivalence checks .

Posted 10/8/2026full-timeUnited StatesMid-LevelSenior💰 $167,700 - $245,200 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in RTL-to-GDSII implementation, including static timing analysis, power integrity, and physical design methodologies. Proficient in optimizing performance and die size while collaborating effectively with cross-functional teams and EDA vendors.

Highest-signal resume keywords

RTL-To-GDSII FlowStatic Timing AnalysisPhysical Design ExperienceEDA Tools ProficiencyHierarchical Design

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Static Timing AnalysisPower Integrity AnalysisTiming ClosureHierarchical DesignTiming ECO ImplementationPython ProgrammingTCL ProgrammingPerl Programming

Tools & Technologies

InnovusTempusPrimeTimeRedhawkVoltusCalibre

Industry Keywords

Physical DesignTiming ConstraintsDesign Tapeouts7nm Process Technology5nm Process Technology3nm Process Technology

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Perform RTL-to-GDSII implementation, including hierarchical floorplanning, place and route, static timing analysis, power integrity, and equivalence checks
Optimize performance and die size
Analyze tool flows and methodologies, identify efficiency gaps, and implement enhancements
Collaborate with RTL, DFT, implementation, EDA vendors, and tool/flow teams
Guide clock tree synthesis strategies and provide feedback to implementation teams
Execute STA setup, convergence methodologies, and sign-off processes across multi-mode, multi-corner scenarios
Complete Timing ECO implementation using Tweaker/PrimeTime-based flows
Contribute to STA methodology automation
Evaluate timing methodologies and tools across technologies and design types

Requirements

What you’ll need

Bachelor’s Degree in Electrical Engineering with 6+ years of Physical Design experience, or Master’s Degree in Electrical Engineering with 4+ years of Physical Design experience, or PhD in Electrical Engineering with 2+ years of Physical Design experience
Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies
Experience with EDA tools such as Innovus, Tempus/PrimeTime, Redhawk/Voltus, or Calibre
Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis
Experience with static timing analysis concepts, timing constraints and exceptions, and corners/voltage definitions
Experience with Python, TCL, or Perl programming

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available, vesting following continued employment
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco policies