ASIC Physical Design Lead

Cisco

. Develop fullchip floorplans based on design architecture, foundry integration guidelines, and IP placement constraints .

Posted 11/4/2026full-timeUnited StatesSenior💰 $186,900 - $267,700 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in Fullchip Floorplanning, RTL-to-GDSII Implementation, and Physical Design methodologies, with a strong focus on optimizing performance, power, and die size. Proficient in collaborating with cross-functional teams and utilizing EDA tools to enhance design efficiency.

Highest-signal resume keywords

Fullchip FloorplanningRTL-to-GDSII FlowEDA Tools (Innovus, Tempus, Redhawk, Calibre)Static Timing AnalysisLow-Power Design Methodologies (UPF)

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Physical DesignHierarchical DesignTiming ClosurePower Integrity AnalysisCustom Chip-Level ClocksPython ProgrammingAI Tools UtilizationClock Mesh ImplementationPower Grid PlanningDesign Tapeouts

Tools & Technologies

InnovusTempusPrimeTimeRedhawkVoltusCalibrePegasus

Industry Keywords

Electrical Engineering7nm Process Technology5nm Process Technology3nm Process TechnologyDesign ArchitectureFoundry IntegrationIP Placement ConstraintsStatic Timing ConstraintsPost-Silicon ValidationSignoff Methodologies

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Develop fullchip floorplans based on design architecture, foundry integration guidelines, and IP placement constraints
Collaborate with system and package design teams to incorporate requirements into fullchip floorplans
Perform hierarchical implementation, including partitioning, pin assignment, clock planning, and bump planning
Implement fullchip clock mesh and Flex-HTree methods
Execute RTL-to-GDSII implementation, including floorplanning, power-grid planning, place and route, static timing analysis, power integrity, physical verification, and equivalence checks
Optimize performance, power, and die size
Analyze tool flows and methodologies, identify efficiency gaps, and implement enhancements
Collaborate with RTL, DFT, implementation, EDA vendor, and tool/flow teams
Work with foundry and standard-cell IP vendors to define and validate signoff methodologies
Adjust signoff methodologies based on post-silicon validation feedback
Use AI tools to improve productivity

Requirements

What you’ll need

Bachelor’s Degree in Electrical Engineering with 8+ years of Physical Design experience, or Master’s Degree in Electrical Engineering with 6+ years of Physical Design experience, or PhD in Electrical Engineering with 3+ years of Physical Design experience
Experience working on Fullchip activities
Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies
Experience with EDA tools such as Innovus, Tempus/PrimeTime, Redhawk/Voltus, or Calibre/Pegasus
Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis
Experience with static timing analysis, timing constraints and exceptions, and corner/voltage definitions
Experience in Fullchip floor-planning and power grid planning
Experience with custom chip-level clocks using H-Tree or Mesh
Python experience
Experience using AI tools with accurate prompts
Proficiency in low-power design methodologies using UPF

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available, vesting following continued employment
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid birthday day off
Paid year-end holiday shutdown
4 paid personal wellness days
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward annually
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses may be available for non-sales roles