ASIC Post Silicon DFT Technical Leader

Cisco

. Work in the Silicon One development organization as a senior ASIC post-silicon DFT Lead .

Posted 10/13/2026full-timeUnited StatesSenior💰 $177,600 - $257,400 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in post-silicon DFT leadership, driving requirements and processes from design to production. Proficient in Verilog design, gate-level simulation, and ATE patterns to ensure high-quality networking chip development.

Highest-signal resume keywords

Post-Silicon ValidationDFT LeadershipGate-Level SimulationVerilog DesignATE Patterns

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Post-Silicon ValidationDFT RequirementsGate-Level SimulationDebuggingVerilog DesignCustom DFT LogicTest ArchitectureStatic Timing AnalysisP1687Functional Verification

Tools & Technologies

VCSATE Patterns

Certifications & Qualifications

Bachelor's Degree in Electrical EngineeringMaster's Degree in Computer Engineering

Industry Keywords

ASICNetworking ChipsProduction ScalabilityYield/Reliability LearningsRamp AccelerationDFT CAD Development

About the role

Key responsibilities & impact

Work in the Silicon One development organization as a senior ASIC post-silicon DFT Lead
Collaborate with post-silicon product engineering, Reliability, Board, package, functional test, and system teams
Understand and define the post-silicon bring-up-to-production roadmap
Drive DFT requirements early in the design cycle
Lead the post-silicon DFT team
Help craft next-generation networking chips
Drive the post-silicon and quality processes through the entire production phase from the DFT design side

Requirements

What you’ll need

Bachelor's or Master's Degree in Electrical or Computer Engineering required
At least 12 years of experience
Prior experience in post-silicon validation, hardware bring-up, yield/reliability learnings, ramp acceleration, FA efficiency, and production scalability
Prior experience working with DFT teams and post-silicon validation from initial bring-up to high-volume production
Experience with gate-level simulation and debugging with VCS and other simulators
Post-silicon validation and debug experience
Ability to work with ATE patterns and P1687
Verilog design experience, developing custom DFT logic and IP integration (preferred)
Familiarity with functional verification (preferred)
DFT CAD development involving test architecture, methodology, and infrastructure (preferred)
Test static timing analysis (preferred)

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year for non-exempt employees
Flexible vacation time off program for exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco policies