Design Verification Technical Leader

Cisco

. Define and lead verification methodology and standards across multiple projects .

Posted 10/23/2026full-timeUnited StatesSenior💰 $192,400 - $275,800 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in ASIC Design Verification, leading verification methodologies, and optimizing performance across multiple projects. Proficient in debugging complex silicon issues and mentoring verification teams to enhance technical skills and execution.

Highest-signal resume keywords

ASIC Design Verification ExperienceSystemVerilog ProficiencyUVM ExpertiseScripting and Automation SkillsLeadership in Verification Projects

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

ASIC Design VerificationSystemVerilogUVMPythonPerlTCLShell ScriptsFormal VerificationVerilogDebugging

Soft Skills

MentoringCollaborationInfluencing Design

Tools & Technologies

VeloceHAPSEmulation PlatformsPrototyping Platforms

Industry Keywords

High-Speed IPsSerDesD2D PHYODSPCPU SubsystemsProtocolsEthernetUCIEUALSPI/I2C

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Define and lead verification methodology and standards across multiple projects
Coordinate verification activities across multiple sites
Lead block- and chip-level verification for high-speed IPs including ODSP, D2D IP, SerDes XSR/PAM4, integrated drivers/TIA, and control functions
Review specifications and participate in design reviews
Influence architecture for testability and verification efficiency
Mentor and coach verification engineers
Drive continuous improvement in technical skills and execution
Debug complex silicon and system-level issues during bring-up phases
Support post-silicon bring-up
Optimize integration and performance

Requirements

What you’ll need

Bachelor’s degree in Electrical or Computer Engineering and 8+ years of ASIC Design Verification experience, or Master’s degree in Electrical or Computer Engineering and 6+ years of ASIC Design experience, or PhD in Electrical or Computer Engineering and 3+ years of ASIC Design Verification experience
Experience with SystemVerilog, UVM, and verification methodologies
Experience owning and delivering verification for large-scale SoCs or subsystems
Experience leading verification teams or projects
Experience in scripting and automation using Python, Perl, TCL, or Shell Scripts
Strong UVM experience for scalable, reusable, coverage-driven verification environments
Expertise in verification of SerDes IP, D2D PHY IP, ODSP, integrated transceiver features, CPU subsystems, and protocols including Ethernet, UCIE, UAL, and SPI/I2C
Experience influencing design for testability and verification
Proven troubleshooting and debugging experience
Experience with Formal Verification and HDLs such as Verilog/SystemVerilog
Experience with emulation and prototyping platforms such as Veloce and HAPS
Experience collaborating with architecture and design teams on verification strategy

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available, vesting following continued employment
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for eligible non-sales roles
Performance-based incentive pay for employees on sales plans