DFT Engineer – Cisco Silicon One

Cisco

. Develop and implement DFT features to ensure high-quality, testable, and manufacturable designs.

Posted 10/15/2026full-timeTel Aviv-Yafo • IsraelMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in DFT methodologies, including ATPG, scan compression, and memory BIST, to enhance test coverage and efficiency throughout the silicon lifecycle. Proven ability to lead debugging efforts and establish best practices for high-quality, manufacturable designs.

Highest-signal resume keywords

DFT MethodologiesAutomatic Test Pattern Generation (ATPG)Silicon DebugScan InsertionBoundary Scan

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

DFT Features DevelopmentTest Coverage ImprovementRoot-Cause AnalysisManufacturable DesignsPre-Silicon DesignPost-Silicon DebugProduction QualificationMemory BIST TechniquesScan CompressionSilicon Lifecycle Collaboration

Soft Skills

Excellent CommunicationPresentation SkillsAttention to DetailAdaptability

Certifications & Qualifications

B.Sc. in Electrical Engineering

Industry Keywords

Silicon SolutionsHigh-Volume ProductionDFT Best PracticesSystem-Level UnderstandingNetworking

About the role

Key responsibilities & impact

Develop and implement DFT features to ensure high-quality, testable, and manufacturable designs.
Contribute to the full product cycle, from pre-silicon design to post-silicon debug and production qualification.
Collaborate across multiple hardware teams throughout the silicon lifecycle.
Implement ATPG, scan compression, and memory BIST techniques to improve test coverage and efficiency.
Lead debugging and root-cause analysis of silicon failures to improve yield and reliability.
Establish DFT methodologies and best practices to improve the efficiency of future designs.

Requirements

What you’ll need

B.Sc. in Electrical Engineering or a related field.
3+ years of hands-on experience with one or more DFT domains, such as scan insertion, BIST, or boundary scan, silicon debug.
Experience with Automatic Test Pattern Generation (ATPG) methodologies.
Strong ability to establish and refine DFT methodologies from design phase to high-volume production.
Ability to quickly learn new concepts and adapt to evolving technologies.
Excellent communication and presentation skills.
Strong attention to detail and system-level understanding of networking and silicon solutions.