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Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Expertise in managing the end-to-end PIC and EIC tape-out lifecycle, with a strong focus on process integration, qualification, and high-volume manufacturing. Proficient in applying design-for-manufacturing principles and leading cross-functional teams in chip development and foundry engagement.
Highest-signal resume keywords
PhD Or MS In Electrical EngineeringChip Development ExperienceProcess Qualification ExpertiseIC Design Tools ProficiencyHigh-Volume Production Success
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
Process IntegrationProcess QualificationRoot-Cause AnalysisDesign Of ExperimentsWafer-To-Wafer IntegrationDie-To-Wafer IntegrationHybrid BondingThin-Wafer ProcessingDesign-For-Manufacturing PrinciplesDesign-For-Reliability Frameworks
Soft Skills
Cross-Functional Team LeadershipVendor Relationship ManagementProject Leadership
Tools & Technologies
Cadence VirtuosoSynopsysKlayout
Industry Keywords
PIC FabricationEIC IntegrationSiPh PlatformsCMOS PlatformsNPO ArchitecturesCPO Architectures
About the role
Key responsibilities & impact- Manage the end-to-end PIC and EIC tape-out lifecycle from PDK engagement through DRC sign-off, process integration, and process qualification
- Drive bring-up of electronic-photonic integration technology platforms with internal design and external foundry teams
- Develop, modify, and optimize photonic and electronic process flows across SiPh and CMOS platforms
- Conceptualize and execute critical process modules using design-for-manufacturing principles
- Ensure robust process windows and high yield from initial integration through high-volume manufacturing ramp
- Lead and optimize wafer-scale EIC-PIC integration using Wafer-to-Wafer and Die-to-Wafer methods
- Focus on co-design and co-fabrication strategies
- Execute root-cause analysis and Design of Experiments to address failure mechanisms
- Apply design-for-reliability frameworks to eliminate failure modes early
- Drive process qualification
Requirements
What you’ll need- PhD or MS in Electrical Engineering, Optics, Photonics, or a related field
- 4+ years of validated experience in chip development, foundry engagement, and process qualification
- Demonstrated success in high-volume production environments
- Knowledge of DFM, DFR, and DFT principles applied to PIC and EIC fabrication, integration, and characterization
- Proficiency in IC design tools including Cadence Virtuoso, Synopsys, and Klayout
- Direct experience working with external foundries on process bring-up is highly desired
- Hands-on experience with hybrid bonding and thin-wafer processing is preferred
- Familiarity or hands-on experience with NPO or CPO architectures is a plus
- Ability to work in cross-functional technical teams and lead vendor/foundry relationships
- Ability to contribute to and lead projects within matrixed, geographically distributed technical teams
Benefits
Comp & perks- Medical, dental and vision insurance
- 401(k) plan with a Cisco matching contribution
- Paid parental leave
- Short- and long-term disability coverage
- Basic life insurance
- Cisco restricted stock unit grants may be available
- 10 paid holidays per full calendar year
- 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday
- Paid year-end holiday shutdown
- 4 paid days off for personal wellness
- 16 days of paid vacation time per full calendar year for non-exempt employees
- Flexible vacation time off program for exempt employees
- 80 hours of sick time off provided on hire date and each January 1st thereafter
- Up to 80 hours of unused sick time carried forward
- Additional paid time away for critical or emergency family issues
- Optional 10 paid volunteer days per full calendar year
- Annual bonuses for non-sales roles, subject to Cisco’s policies
- Performance-based incentive pay for sales-plan employees
