Hardware ASIC Packaging SI/PI Simulation and Design Lead

Cisco

. Develop, document, and implement design rules for ultra-high-speed signaling .

Posted 10/22/2026full-timeUnited StatesSenior💰 $186,900 - $267,700 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in signal and power integrity with a strong foundation in high-speed design principles, including Transmission Line Theory and advanced packaging techniques. Proficient in using industry-standard EDA tools for simulations and validations while effectively collaborating with multidisciplinary teams.

Highest-signal resume keywords

Signal Integrity ExpertisePower Integrity AnalysisHigh-Speed Design PrinciplesEDA Tool ProficiencyMentorship and Team Collaboration

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

Signal IntegrityPower IntegrityHigh-Speed DesignTransmission Line TheoryElectromagneticsPAM4 SerDes ArchitecturesSPICE AnalysisVector Network AnalysisChannel ModelingImpedance Network Analysis

Soft Skills

Technical CommunicationMentoringCollaboration

Tools & Technologies

Cadence SigrityAnsys HFSSKeysight ADSCadence APDAnsys EM

Industry Keywords

ASIC DesignHigh-Speed Memory InterfaceDie-to-Die InterfacesCoWoSEMIBInterposer-Based DesignsPhysical Design ValidationPost-Layout Extraction

About the role

Key responsibilities & impact

Develop, document, and implement design rules for ultra-high-speed signaling
Analyze substrate signal integrity and power integrity across interposer, substrate, and PCB
Collaborate with layout teams to develop optimal SI/PI solutions
Design, document, and develop ASIC packages for high-volume, high-quality release
Perform post-layout extraction and reporting
Collaborate with system partners, vendors, and design leads to resolve complex technical issues
Define processes, methods, and tools for complex ASIC/package development
Lead or participate in chip architecture discussions and high-performance ASIC design
Review intricate IC and analog/mixed-signal circuit designs
Mentor and support the signal integrity team and junior engineers
Influence packaging and hardware teams to meet technical specifications
Promote design reviews, postmortems, and continuous improvement across multidisciplinary engineering teams

Requirements

What you’ll need

Bachelor’s degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience, or Master’s degree in Electrical Engineering and 6+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 3+ years of relevant signal and power integrity experience
Experience with high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis
Experience applying high-speed design principles to 56G PAM4 SerDes architectures, channel modeling, and BER prediction
Experience with pre- and post-layout SI/PI simulations
Proficiency with industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS
Experience conducting detailed layout reviews and physical design validation using Cadence APD and Ansys EM flows
Experience with SPICE for circuit-level analysis, signal modeling, and performance validation
Experience articulating technical concepts to diverse audiences, verbally and in writing
Experience with HBM or high-speed memory interface SI
Experience with die-to-die interfaces such as UCIe or proprietary interfaces
Experience with advanced packaging such as CoWoS, EMIB, and interposer-based designs
Experience with Vector Network Analysis
Experience with IBIS

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
Paid birthday day off
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco’s policies
Performance-based incentive pay for sales-plan employees