Hardware ASIC Packaging SI/PI Simulation and Design Lead

Cisco

. Develop, document, and implement design rules for ultra-high-speed signaling while meeting power, performance, and area goals .

Posted 10/22/2026full-timeSan Jose • California • United StatesSenior💰 $186,900 - $267,700 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in signal and power integrity with a strong foundation in high-speed design principles, including Transmission Line Theory and electromagnetics. Proficient in using industry-standard EDA tools for ASIC/package development and validation.

Highest-signal resume keywords

Signal Integrity AnalysisPower Integrity AnalysisHigh-Speed Design PrinciplesEDA Tools ProficiencyASIC Package Development

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Signal IntegrityPower IntegrityHigh-Speed DesignTransmission Line TheoryElectromagneticsPAM4 SerDes ArchitecturesPre- and Post-Layout SimulationsCircuit-Level AnalysisPerformance ValidationLayout Reviews

Soft Skills

MentoringTechnical Communication

Tools & Technologies

Cadence SigrityAnsys HFSSKeysight ADSCadence APDAnsys EMSPICEVector Network Analysis

Industry Keywords

ASIC DevelopmentHigh-Speed Memory InterfaceDie-to-Die InterfacesAdvanced PackagingCoWoSEMIBInterposer-Based Designs

About the role

Key responsibilities & impact

Develop, document, and implement design rules for ultra-high-speed signaling while meeting power, performance, and area goals
Analyze substrate signal integrity and power integrity
Collaborate with layout teams to optimize solutions across interposer, substrate, and PCB
Design, document, and develop ASIC packages for high-volume, high-quality release
Perform post-layout extraction and reporting
Collaborate with system partners, vendors, and design leads to achieve combined power and signal integrity
Resolve complex technical issues using advanced technology design rules
Define processes, methods, and tools for complex ASIC/package development
Lead or participate in chip architecture discussions and define, architect, and design high-performance ASICs
Review intricate IC and analog/mixed-signal circuit designs
Mentor and support the signal integrity team and junior engineers
Influence packaging and hardware teams to meet technical specifications and develop innovative solutions
Promote design reviews, postmortems, and continuous improvement across multidisciplinary engineering teams

Requirements

What you’ll need

Bachelor's degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 6+ years of relevant signal and power integrity experience, or PhD in Electrical Engineering and 3+ years of relevant signal and power integrity experience
Experience with high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis
Experience applying high-speed design principles to 56G PAM4 SerDes architectures, channel modeling, and BER prediction
Experience with pre- and post-layout SI/PI simulations
Proficiency with industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS
Experience conducting detailed layout reviews and physical design validation
Experience with Cadence APD and Ansys EM flows
Experience with SPICE for circuit-level analysis, signal modeling, and performance validation
Preferred: articulating technical concepts to diverse audiences verbally and in writing
Preferred: experience with HBM or high-speed memory interface SI
Preferred: experience with UCIe or proprietary die-to-die interfaces
Preferred: experience with advanced packaging such as CoWoS, EMIB, and interposer-based designs
Preferred: experience with Vector Network Analysis
Preferred: experience with IBIS

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available, subject to eligibility
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
Paid birthday day off
Paid year-end holiday shutdown
4 paid personal wellness days
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco policies
Performance-based incentive pay for sales-plan employees
Opportunities for growth and professional development through a worldwide network of experts