Hardware ASIC Packaging SI/PI Simulation and Design Lead

Cisco

. Develop, document, and implement design rules for ultra-high-speed signaling .

Posted 10/14/2026full-timeRemote • United StatesSenior💰 $186,900 - $267,700 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in signal and power integrity analysis, high-speed design principles, and ASIC package development. Proficient in using industry-standard EDA tools for simulations and layout validation while mentoring junior engineers and collaborating across multidisciplinary teams.

Highest-signal resume keywords

Signal Integrity AnalysisPower Integrity AnalysisHigh-Speed Design PrinciplesEDA Tool ProficiencyASIC Package Development

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Signal IntegrityPower IntegrityHigh-Speed DesignTransmission Line TheoryElectromagneticsPAM4 SerDes ArchitecturesPre- and Post-Layout SimulationsSPICE AnalysisChannel ModelingBER Prediction

Soft Skills

MentoringCollaborationTechnical Communication

Tools & Technologies

Cadence SigrityAnsys HFSSKeysight ADSCadence APDAnsys EM

Industry Keywords

IC DesignAnalog Circuit DesignMixed-Signal Circuit DesignAdvanced PackagingHigh-Speed Memory InterfaceVector Network AnalysisIBISCoWoSEMIBInterposer-Based Designs

About the role

Key responsibilities & impact

Develop, document, and implement design rules for ultra-high-speed signaling
Analyze substrate signal integrity and power integrity across interposer, substrate, and PCB
Collaborate with layout teams to develop optimal packaging solutions
Design, document, and develop ASIC packages for high-volume, high-quality release
Perform post-layout extraction and reporting
Collaborate with system partners, vendors, and design leads to resolve complex technical issues
Define processes, methods, and tools for complex ASIC/package developments
Lead or participate in chip architecture discussions and high-performance ASIC design
Review intricate IC and analog/mixed-signal circuit designs
Mentor and support the signal integrity team and junior engineers
Influence packaging and hardware teams to meet technical specifications
Promote design reviews, postmortems, and continuous improvement across multidisciplinary engineering teams

Requirements

What you’ll need

Bachelor's degree in Electrical Engineering and 8+ years of relevant signal and power integrity experience, or Master's degree in Electrical Engineering and 6+ years of relevant experience, or PhD in Electrical Engineering and 3+ years of relevant experience
Experience with high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis
Experience applying high-speed design principles to 56G PAM4 SerDes architectures, channel modeling, and BER prediction
Experience with pre- and post-layout SI/PI simulations
Proficiency with industry-standard EDA tools such as Cadence Sigrity, Ansys HFSS, and Keysight ADS
Experience conducting detailed layout reviews and physical design validation using Cadence APD and Ansys EM flows
Experience with SPICE for circuit-level analysis, signal modeling, and performance validation
Preferred: ability to articulate technical concepts to diverse audiences
Preferred: experience with HBM or high-speed memory interface SI
Preferred: experience with UCIe or proprietary die-to-die interfaces
Preferred: experience with advanced packaging such as CoWoS, EMIB, and interposer-based designs
Preferred: experience with Vector Network Analysis
Preferred: experience with IBIS

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available, vesting following continued employment
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
Paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco policies
Performance-based incentive pay for sales-plan employees