Senior ASIC Analog Layout Engineer

Cisco

. Architect physical layouts for high-speed optical interconnects .

Posted 10/5/2026full-timeUnited StatesSenior💰 $149,100 - $218,100 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in architecting high-speed optical interconnects and optimizing complex analog and mixed-signal layouts, with a strong focus on physical verification and custom layout design. Proficient in managing block-to-top integration and executing physical signoff flows while mentoring engineering talent.

Highest-signal resume keywords

Custom Analog Layout ExperienceCadence Virtuoso ProficiencyPhysical Verification ExpertiseScripting Capabilities in PythonStrong Command of Physical Signoff Flows

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Block-Level Layout DesignParasitic ControlThermal ManagementSignal IntegrityDevice-Level Layout TechniquesCustom Layout DesignASIC/SoC Tapeout ProcessesPost-Layout ExtractionEM/IR AnalysisFloorplanning

Soft Skills

Mentoring Engineering TalentCross-Functional Team Collaboration

Tools & Technologies

Cadence VirtuosoCalibreEDA ToolsLinux Environment

Industry Keywords

High-Speed Optical InterconnectsFINFET Technology3nm Process5nm Process7nm ProcessPhysical Execution StandardsDesign Methodologies

Tech Stack

Tools & technologies

LinuxPerlPython

About the role

Key responsibilities & impact

Architect physical layouts for high-speed optical interconnects
Own block-to-top integration for 100G, 200G, and 400G per lambda architectures
Build and optimize complex analog and mixed-signal layouts
Drive execution from concept and floorplanning through post-layout extraction, sign-off, tapeout, and post-silicon bring-up
Solve parasitic, signal integrity, and thermal tradeoffs with circuit design, packaging, and CAD teams
Shape design methodologies
Mentor engineering talent
Improve physical execution standards across the group

Requirements

What you’ll need

Bachelor’s degree plus 7 years of related experience, or Master’s degree plus 4 years of related experience, or PhD plus 1 year of related experience
Prior experience supporting block-level layout efforts through tapeout
Prior experience in physical verification and custom layout design
Custom analog layout experience in FINFET 7nm, 5nm, or 3nm
Prior experience with Cadence Virtuoso or similar custom layout tools
Experience with device-level layout techniques including matching, symmetry, shielding, common-centroid, interdigitation, guard rings, and isolation structures
Knowledge of parasitic control, thermal management, and signal integrity
Experience with Cadence Virtuoso and Calibre or equivalent EDA tools in a Linux environment
Strong command of physical signoff flows including DRC, LVS, ERC, parasitic extraction, and EM/IR analysis
Experience with ASIC/SoC tapeout processes
Scripting capabilities in Python, Perl, or TCL for layout automation
Experience working with cross-functional teams across multi-location teams
Custom analog experience in TSMC 2nm or below is a plus

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation per full calendar year for non-exempt full-time employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco policies