Senior ASIC DFT DV Engineer

Cisco

. Create thorough test plans and develop test benches to verify comprehensive DFT architecture .

Posted 10/13/2026full-timeUnited StatesSenior💰 $167,700 - $245,200 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in developing test plans and test benches for DFT architecture, with a strong focus on debugging and validation of silicon devices. Proficient in utilizing advanced methodologies and tools to ensure effective test strategies and solutions.

Highest-signal resume keywords

Test PlanningTestbench Development Using System VerilogDebugging Using DVE/VerdiTCL, Python, or Perl ProficiencyKnowledge of JTAG Protocol and Scan Architecture

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Test PlanningTestbench DevelopmentDebuggingSystem VerilogTCLPythonPerlUVMDVE/VerdiDFT Architecture

Soft Skills

CollaborationProblem-SolvingInnovative ThinkingEfficiency

Tools & Technologies

DVEVerdiATE ScreeningPost-Silicon Validation Flows

Industry Keywords

DFTJTAG ProtocolScan ArchitectureMBISTBoundary Scan

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Create thorough test plans and develop test benches to verify comprehensive DFT architecture
Support ATE screening, in-system test, debug and diagnostics needs
Collaborate with design, design-verification and PD teams to integrate and validate test logic
Contribute to implementation and post-silicon validation flows
Develop innovative hardware DFT and test strategies for new silicon device models, bare die and stacked die
Drive reusable test and debug methodologies and standards
Craft solutions and debug efficiently

Requirements

What you’ll need

Bachelor’s in Electrical Engineering or equivalent with at least 7+ years of experience, or Master’s with 4+ years of experience
Prior experience in test planning based on complex design specifications
Prior experience in testbench development using System Verilog
Experience debugging using DVE/Verdi
Experience with TCL, Python or Perl
UVM and advanced System Verilog knowledge preferred
Knowledge of JTAG protocol, scan architecture, MBIST and boundary scan preferred

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Potential Cisco restricted stock unit grants, subject to eligibility
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco’s policies