Senior ASIC Physical Design Engineering Technical Leader

Cisco

. Perform RTL-to-GDSII implementation, including logic synthesis, hierarchical floorplanning, place and route, static timing analysis, power integrity, and equivalence checks .

Posted 10/27/2026full-timeUnited StatesSenior💰 $214,100 - $309,800 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in RTL-to-GDSII implementation, including static timing analysis, physical design, and optimization techniques. Proficient in utilizing EDA tools and methodologies to enhance design efficiency and ensure timing closure across advanced process technologies.

Highest-signal resume keywords

RTL-To-GDSII ImplementationStatic Timing AnalysisEDA Tools (Innovus, Primetime, Tempus, Redhawk, Voltus, Calibre)Physical Design ExperienceHierarchical Design

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Logic SynthesisHierarchical FloorplanningPlace And RoutePower Integrity AnalysisTiming ClosureTiming ConstraintsFullchip ActivitiesECO ImplementationPython ProgrammingTCL Programming

Certifications & Qualifications

Bachelor’s Degree In Electrical EngineeringMaster’s Degree In Electrical EngineeringPhD In Electrical Engineering

Industry Keywords

Fullchip DesignTiming MethodologiesClock Tree SynthesisPower Grid Planning7nm Process Technology5nm Process Technology3nm Process Technology

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Perform RTL-to-GDSII implementation, including logic synthesis, hierarchical floorplanning, place and route, static timing analysis, power integrity, and equivalence checks
Optimize performance and die size
Analyze existing tool flows and methodologies, identify efficiency gaps, and implement enhancements
Collaborate with RTL, DFT, implementation, EDA vendor, and tool/flow teams
Guide Clock Tree Synthesis strategies and provide actionable feedback to implementation teams
Execute STA setup, convergence methodologies, and sign-off processes across multi-mode, multi-corner scenarios
Complete functional and timing ECO implementation using industry-standard flows
Contribute to STA methodology automation
Evaluate timing methodologies and tools across technologies and design types

Requirements

What you’ll need

Bachelor’s Degree in Electrical Engineering with 12+ years of Physical Design experience, or Master’s Degree in Electrical Engineering with 8+ years of Physical Design experience, or PhD in Electrical Engineering with 5+ years of Physical Design experience
Experience working on Fullchip activities
Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies
Experience working with EDA tools such as Innovus, Primetime/Tempus, Redhawk/Voltus and Calibre
Experience with hierarchical design, timing closure, physical convergence, and power integrity analysis
Experience with static timing analysis, timing constraints and exceptions, and corners/voltage definitions
Experience in Fullchip floor-planning and power grid planning
Experience with custom clock (H-Tree or Mesh) at chip level
Experience with Python, TCL, or Perl programming

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available, subject to eligibility and continued employment
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward annually
Additional paid time away for critical or emergency family issues
Optional 10 paid days per full calendar year to volunteer
Annual bonuses for non-sales roles, subject to Cisco’s policies
Performance-based incentive pay for sales-plan employees