Senior ASIC Physical Design Lead

Cisco

. Create fullchip floorplans by understanding design architecture, foundry integration guidelines and IP placement constraints .

Posted 10/20/2026full-timeUnited StatesSenior💰 $214,100 - $309,800 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in Physical Design, including RTL-to-GDSII implementation, fullchip floorplanning, and power integrity analysis. Proficient in utilizing EDA tools and methodologies to optimize design performance and collaborate effectively with cross-functional teams.

Highest-signal resume keywords

Physical Design ExperienceRTL-To-GDSII FlowEDA Tools ProficiencyLow-Power Design MethodologiesHierarchical Design Expertise

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Fullchip FloorplanningStatic Timing AnalysisPower Integrity AnalysisCustom Clock H-TreePython ProgrammingTiming ClosurePartitioningPin AssignmentPower-Grid PlanningPhysical Design Convergence

Tools & Technologies

InnovusTempusPrimeTimeRedHawkVoltusCalibrePegasusAI Tools

Certifications & Qualifications

Bachelor’s Degree in Electrical EngineeringMaster’s Degree in Electrical EngineeringPhD in Electrical Engineering

Industry Keywords

Foundry Integration GuidelinesDesign ArchitectureSignoff MethodologiesDesign Tapeouts7nm Process Technology5nm Process Technology3nm Process TechnologyDFTTool/Flow TeamsIncremental Enhancements

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Create fullchip floorplans by understanding design architecture, foundry integration guidelines and IP placement constraints
Collaborate with system and package design teams to incorporate requirements into fullchip floorplans
Perform hierarchical implementation, including partitioning, pin assignment, clock planning and bump planning
Apply fullchip clock mesh and Flex-HTree methods
Execute RTL-to-GDSII implementation, including floorplanning, power-grid planning, placement and routing, static timing analysis, power integrity, physical verification and equivalence checks
Optimize performance, power and die size
Analyze existing tool flows and methodologies, identify efficiency gaps, and implement incremental or transformative enhancements
Work with RTL, DFT, implementation, EDA vendors, and tool/flow teams to enable design methodology
Define signoff methodologies with foundry and standard cell IP vendors
Validate and adjust signoff methodologies based on post-silicon validation feedback
Use AI tools to improve productivity

Requirements

What you’ll need

Bachelor’s Degree in Electrical Engineering with 12+ years of Physical Design experience, or Master’s Degree in Electrical Engineering with 8+ years of Physical Design experience, or PhD in Electrical Engineering with 5+ years of Physical Design experience
Experience with RTL2GDSII flow and design tapeouts in 7nm/5nm/3nm or below process technologies
Experience with EDA tools such as Innovus, Tempus/PrimeTime, RedHawk/Voltus, or Calibre/Pegasus
Experience with fullchip activities including floor-planning, power-grid planning, partitioning and pin assignment
Experience with hierarchical design, timing closure, physical design convergence, and power integrity analysis
Experience with static timing analysis, timing constraints and exceptions, and corners/voltage definitions
Experience with custom clock H-Tree or Mesh at chip level
Experience with Python
Experience using AI tools and giving accurate prompts
Proficiency in low-power design methodologies using UPF
Experience working with foundry and standard cell IP vendors
Ability to work with RTL, DFT, implementation, EDA vendor, and tool/flow teams

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Cisco restricted stock unit grants may be available, subject to continued employment and vesting periods
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation per full calendar year for non-exempt employees
Flexible vacation time off program with no defined limit for eligible exempt employees, subject to availability and business limitations
80 hours of sick time off provided on hire and each January 1st, with up to 80 unused hours carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for eligible non-sales roles
Performance-based incentive pay for eligible sales-plan employees
Opportunities to grow and build at Cisco
AI tools and productivity-focused work environment