FREE ACCESS
5,000–10,000 jobs/day
See all jobs on Scoutfield
Search thousands of fresh jobs every day.
Discover
- Fresh listings
- Fast filters
- No subscription required
Create a free account and start exploring right away.
Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in DFT methodologies, including ATPG, scan insertion, and BIST, to enhance test coverage and efficiency throughout the silicon lifecycle. Proven ability to lead debugging efforts and establish best practices for high-quality, manufacturable designs.
Highest-signal resume keywords
DFT MethodologiesAutomatic Test Pattern Generation (ATPG)Silicon DebugScan InsertionBoundary Scan
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
DFT Features DevelopmentTest Coverage ImprovementRoot-Cause AnalysisManufacturable DesignsMemory BIST Techniques
Soft Skills
Excellent CommunicationAttention to DetailAdaptability
Certifications & Qualifications
B.Sc. in Electrical Engineering
Industry Keywords
Silicon LifecyclePre-Silicon DesignPost-Silicon DebugProduction QualificationHigh-Volume Production
About the role
Key responsibilities & impact- Develop and implement DFT features to ensure high-quality, testable, and manufacturable designs
- Contribute to the full product cycle, from pre-silicon design to post-silicon debug and production qualification
- Collaborate across multiple hardware teams throughout the silicon lifecycle
- Implement ATPG, scan compression, and memory BIST techniques to improve test coverage and efficiency
- Lead debugging and root-cause analysis of silicon failures to improve yield and reliability
- Establish DFT methodologies and best practices to improve the efficiency of future designs
Requirements
What you’ll need- B.Sc. in Electrical Engineering or a related field
- 5+ years of hands-on experience with one or more DFT domains, such as scan insertion, BIST, boundary scan, or silicon debug
- Experience with Automatic Test Pattern Generation (ATPG) methodologies
- Strong ability to establish and refine DFT methodologies from design phase to high-volume production
- Ability to quickly learn new concepts and adapt to evolving technologies
- Excellent communication and presentation skills
- Strong attention to detail and system-level understanding of networking and silicon solutions
Benefits
Comp & perks- Opportunities to grow and build within Cisco's worldwide network of experts
- Collaborative team environment
- Work on innovative hardware platforms powering AI-era switching, routing, and wireless products