Signal and Power Integrity Technical Leader

Cisco

. Develop next-generation ASIC packaging .

Posted 10/2/2026full-timeSan Jose • California • United StatesSenior💰 $214,100 - $309,800 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in ASIC packaging design, signal integrity, and power integrity, with a strong focus on high-speed signaling and collaboration across multidisciplinary teams. Proven ability to lead technical discussions and mentor team members while ensuring compliance with performance and area goals.

Highest-signal resume keywords

ASIC Packaging DesignSignal Integrity AnalysisPower Integrity ExperienceHigh-Speed SerDes ArchitecturesLeadership in Technical Teams

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Electrical Engineering DegreeHigh-Speed ASIC Tape-Outs56G PAM4 ExperienceChannel ModelingBER PredictionTransmission Line TheoryScattering Parameters KnowledgeSPICE ProficiencyAdvanced Packaging TechniquesMATLAB or Python Scripting

Soft Skills

MentoringCollaborationInfluencing Technical TeamsContinuous Improvement

Tools & Technologies

Keysight ADSAnsys HFSS/EM FlowCadence APDRaptor-XVector Network AnalysisIBIS

Industry Keywords

ASIC PackagingSignal IntegrityPower IntegrityHigh-Speed Memory InterfaceDie-to-Die Interfaces

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Develop next-generation ASIC packaging
Lead the Silicon Packaging Signal and Power Integrity Team
Define, design, and verify ASIC packaging for Cisco platforms
Develop, document, and implement design rules for ultra-high-speed signaling
Ensure power, performance, and area goals are met
Analyze substrate signal integrity and power integrity
Collaborate with layout teams on solutions across interposer, substrate, and PCB
Design, document, and develop ASIC packages for high-volume, high-quality release
Perform post-layout extraction and reporting
Collaborate with system partners, vendors, and design leads to resolve complex technical issues
Define processes, methods, and tools for complex ASIC/package development
Lead or participate in chip architecture discussions and high-performance ASIC definition, architecture, and design
Review intricate IC and analog/mixed-signal circuit designs
Mentor and support signal integrity team members and junior engineers
Influence packaging and hardware teams to meet technical specifications and deliver innovative solutions
Promote design reviews, postmortems, and continuous improvement across multidisciplinary engineering teams

Requirements

What you’ll need

Bachelor's degree in Electrical Engineering and 10+ years of relevant signal and/or power integrity experience, or Master's degree in Electrical Engineering and 8+ years of relevant experience, or PhD in Electrical Engineering and 5+ years of relevant experience
Experience with multiple high-speed ASIC tape-outs from a package perspective
Experience with 56G PAM4 and above
Experience with high-speed SerDes architectures
Experience with channel modeling
Experience with BER prediction
Knowledge of transmission line theory and electromagnetics
Solid understanding of scattering and impedance network parameters
Hands-on lab experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review
Experience with SPICE
Preferred: experience leading small to medium technical teams
Preferred: experience with advanced nodes (5nm, 3nm and below)
Preferred: experience with HBM or high-speed memory interface SI
Preferred: experience with die-to-die interfaces such as UCIe or proprietary interfaces
Preferred: experience with advanced packaging including CoWoS, EMIB, and interposer-based designs
Preferred: experience with MATLAB or Python scripting
Preferred: experience with Raptor-X
Preferred: experience with Vector Network Analysis
Preferred: experience with IBIS

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short- and long-term disability coverage
Basic life insurance
Grants of Cisco restricted stock units, subject to eligibility
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year for non-exempt employees
Flexible vacation time off program for exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward
Additional paid time away for critical or emergency family issues
Optional 10 paid volunteer days per full calendar year
Annual bonuses for non-sales roles, subject to Cisco policies
Worldwide network of doers and experts
Opportunities to grow and build
Collaborative, empathetic team environment