Senior System-on-Chip Design Engineer

. Develop and execute SoC RTL design, integration, and related RTL design checks .

Posted 9/25/2026full-timeRemote • IndiaSeniorWebsite

Key responsibilities & impact

Develop and execute SoC RTL design, integration, and related RTL design checks
Participate in and contribute to architecture discussions
Work with DFT, Verification, and Physical Design teams
Own parts of the SoC design, including one or more subsystems and full-chip-level design activities
Plan deliverables in line with overall project deliverables
Perform design, frontend, DFT, and verification activities across all stages
Handle chip-level clocking, booting, and low-power design
Conduct PPA analysis and IP evaluations and selection
Collaborate with global teams
Partner with design leads and architects and adhere to best practices
Contribute to SoC design integration and quality checks
Own PPA, design constraints, and Lint/CDC activities as applicable
Work with verification, physical design, DFT, and other functions to achieve production-quality silicon
Train and mentor fresh engineers
Build collaboration with R&D team members and leads across Architecture, SoC, and Implementation
Influence technical strategy and drive innovation in products, technology, and/or patents
Potentially perform ASIC implementation tasks including synthesis, timing constraints, ECOs, STA, power intent implementation and validation, lint, power analysis, CDC/RDC analysis and validation
Potentially perform RTL development and physical design activities from floor-plan definition through place and route
Model and analyze performance, area, power, and system cost tradeoffs for different micro-architectures

What you’ll need

BTech /MTech/ PhD with 10+ years' experience in the semiconductor industry
Experienced team lead or technical manager with experience leading a team in SoC Design and Verification
Experience in wireless standards and connectivity, including signal processing
Experience of SoCs based on ARM Core Architecture, RISC V, Power PC, etc.
Understanding of high-speed peripherals like DDR, PCIe, ENET, UCIe
Familiarity with interfaces like QSPI, I2C, USB
Memory subsystem architecture knowledge
Knowledge of Neural Accelerators, CPUs, ARM subsystems, AXI/APB interfaces
Strong domain knowledge of clocking, system modes, power management, debug, interconnect, security and other architectures
Experience working with Lint, CDC, RDC, Power Aware/Low power design
Power management understanding
Continuous learning and improvement
Pushing the envelope
Chiplet implementation and understanding of System In Package
Knowledge of latest packaging/substrate technologies
Die to Die interfaces knowledge

Comp & perks

Competitive compensation package
Comprehensive paid time off, vacations and sick leaves
Opportunity to join a well-funded fabless AI semiconductor startup
Opportunity to contribute to the growth and momentum of a company disrupting the AI software and hardware co-design space