Silicon Physical Design Engineer V

Fresh Consulting

. Set up and maintain PPRTL and PTPX power analysis flows for average and time-based/peak power .

Posted 11/3/2026contractRemote • United StatesSeniorLead💰 $75 - $115 per hourWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in ASIC power analysis and optimization, including power estimation, scripting, and data analysis. Proficient in using industry-standard tools for power characterization and low power design methodologies.

Highest-signal resume keywords

ASIC Power AnalysisPower Estimation ToolsTCL ScriptingPython ScriptingLow Power Design

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Power Analysis FlowsRTL and Gate-Level SimulationsPPA OptimizationData VisualizationPower ModelingSynthesisPhysical DesignDebugging Simulation IssuesActivity Input ManagementPower Breakdown Analysis

Soft Skills

Clear CommunicationDocumentation Skills

Tools & Technologies

Synopsys ToolsCadence ToolsLinuxExcel-based ScriptingFusion Compiler

Industry Keywords

ASIC DesignPower Trade-offsUPF Power IntentSilicon Power CharacterizationMachine Learning Hardware

Tech Stack

Tools & technologies

LinuxPython

About the role

Key responsibilities & impact

Set up and maintain PPRTL and PTPX power analysis flows for average and time-based/peak power
Generate and manage activity inputs (FSDB/VCD/SAIF) from RTL and gate-level simulations
Handle long-waveform and windowed analysis
Correlate RTL-level power estimates against gate-level signoff power and explain deltas
Produce per-block, per-hierarchy, and per-workload power breakdowns
Identify top power contributors and clock/datapath waste
Recommend and evaluate power reduction opportunities, including clock gating efficiency, datapath gating, memory power, and idle leakage
Automate flows and reporting with TCL, Python, and Make-based build systems
Integrate automation into regression/CI
Document methodology and support design teams in interpreting results
Perform PPA optimization with Fusion Compiler
Perform RTL and netlist-level power analysis
Post-process and script report log files for format conversion, data analysis, and information extraction
Set up, run, debug, and analyze ASIC flows including synthesis, physical design, power, and timing
Implement select blocks at RTL and UPF
Document and communicate findings clearly

Requirements

What you’ll need

10+ years of experience as an ASIC Power Engineer, CAD Engineer, or Physical Design Engineer
Experience with power estimation tools and synthesis, plus some physical design
Knowledge of power trade-offs in design and back-end implementation
Hands-on experience in scripting and data analysis
Hands-on production experience with Synopsys (PPRTL, PTPX/PrimePower, VCS, Verdi, DC, ICC, FC) and/or Cadence (Joules), PowerArtist
Ability to debug simulation-to-power flow issues end to end
Strong scripting skills: TCL, Python, and Excel-based scripting and data post-processing tools, model fitting, data visualization and analysis
Comfortable with Linux and large compute/job-scheduling environments
Experience in low power design, tools, and methodologies, including UPF power intent specifications
Silicon power characterization, including some power modeling/profiling experience at the IP/SoC level
Interest or experience in machine learning hardware for AR/VR products
BS in Electrical Engineering, Computer Science, or equivalent experience
Must work Pacific Time (PST) hours

Benefits

Comp & perks

Employee benefits at 100% including Medical
PTO
Holiday Pay
401K Plan