Fresh Consulting

Mechanical Engineer

• Set up and maintain PPRTL and PTPX power analysis flows for average and time-based/peak power
• Generate and manage activity inputs (FSDB/VCD/SAIF) from RTL and gate-level simulations
• Handle long-waveform and windowed analysis
• Correlate RTL-level power estimates against gate-level signoff power and explain deltas
• Produce per-block, per-hierarchy, and per-workload power breakdowns
• Identify top power contributors and clock/datapath waste
• Recommend and evaluate power reduction opportunities, including clock gating efficiency, datapath gating, memory power, and idle leakage
• Automate flows and reporting with TCL, Python, and Make-based build systems
• Integrate automation into regression/CI
• Document methodology and support design teams in interpreting results
• Perform PPA optimization with Fusion Compiler
• Perform RTL and netlist-level power analysis
• Post-process and script report log files for format conversion, data analysis, and information extraction
• Set up, run, debug, and analyze ASIC flows including synthesis, physical design, power, and timing
• Implement select blocks at RTL and UPF
• Document and communicate findings clearly

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Silicon Physical Design Engineer V