CPU IP Design & Verification Engineer – RISC-V

GlobalFoundries

. Develop RISC-V CPU microarchitecture and SystemVerilog RTL design and development .

Posted 10/23/2026full-timeUnited StatesEntry Level💰 $86,000 - $170,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in RISC-V CPU microarchitecture and SystemVerilog RTL design, with strong analytical and problem-solving skills. Proficient in programming with Python and C/C++, and experienced in CPU verification and simulation processes.

Highest-signal resume keywords

RISC-V CPU MicroarchitectureSystemVerilog RTL DesignPython ProgrammingDigital Logic DesignCPU Verification

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SystemVerilogVerilogCPU FundamentalsDigital Logic DesignProgramming in C/C++ScriptingAssertionsFunctional CoverageSimulationDebugging

Soft Skills

Analytical SkillsProblem-Solving SkillsCommunication SkillsPlanning SkillsOrganizational Skills

Tools & Technologies

GitLinuxAI-Assisted Engineering ToolsFPGAASIC

Industry Keywords

CPU ArchitectureMicroarchitectureInstruction Set ArchitectureCachesMemory Hierarchy

Tech Stack

Tools & technologies

AssemblyLinuxPythonC++

About the role

Key responsibilities & impact

Develop RISC-V CPU microarchitecture and SystemVerilog RTL design and development
Contribute to CPU functions including instruction fetch and decode, execution, load/store, caches and memory interfaces, control and status registers, exceptions, and interrupts
Develop verification tests, assertions, checkers, and functional coverage for CPU features
Run CPU simulations and regressions and debug failures using logs, architectural traces, and waveforms
Support functional and coverage closure through design and verification reviews
Support CPU power, performance, and area analysis and optimization
Develop Python, C/C++, or scripting-based automation to improve design, verification, regression, and debug productivity
Collaborate across architecture, design, verification, performance, and implementation teams to deliver high-quality CPU IP
Perform activities safely and responsibly and support Environmental, Health, Safety & Security requirements and programs

Requirements

What you’ll need

Graduating with a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field from an accredited degree program
Overall GPA of at least 3.0 and proven good academic standing
English fluency, written and verbal
Strong foundation in digital logic design and computer architecture
Coursework, research, internship, or project experience with Verilog or SystemVerilog
Understanding of CPU fundamentals including pipelines, instruction execution, loads/stores, caches, and memory hierarchy
Programming or scripting experience with Python, C/C++, or similar languages
Strong analytical, problem-solving, and debugging skills
Prior related internship or co-op experience
Demonstrated prior leadership experience
Project management skills
Strong written and verbal communication skills
Strong planning and organizational skills
Knowledge of the RISC-V Instruction Set Architecture (ISA)
Experience with SystemVerilog/UVM, assertions, functional coverage, or constrained-random verification
CPU architecture, microarchitecture, FPGA, ASIC, or processor-design project experience
Familiarity with caches, memory subsystems, privilege modes, exceptions, interrupts, or virtual memory
Experience with simulation, waveform debug, Git, and Linux
Exposure to synthesis, lint, clock-domain crossing analysis, formal verification, or timing analysis
Assembly-language programming experience
Interest in using AI-assisted engineering tools

Benefits

Comp & perks

Accelerated training in a fast-paced work environment
Cross-functional working opportunities
Talent mobility
Mentorship
Networking opportunities
Leadership opportunities