GlobalFoundries

Business Analyst

• Design and document business and operating processes, including current-state mapping, target-state design and transition planning
• Support GF’s customer coverage approach by pairing customers with optimal sales and service models
• Support Sales in partner business reviews with performance insights, market and operational intelligence, and data-driven recommendations
• Identify process and system gaps and collaborate with cross-functional teams to simplify workflows and improve efficiency
• Facilitate funnel and partner performance reviews by preparing analysis, framing decisions, capturing actions and driving them to closure
• Automate recurring reporting and manual commercial workflows using low-code and AI-assisted tools
• Prepare written summaries, process documentation and recommendations for senior commercial leadership
• Perform activities safely and support Environmental, Health, Safety & Security requirements and programs

Business Analyst – New College Graduate

Affiliate Manager

• Analyze business data, improve processes, create training materials and support partner performance reviews
• Collect, organize and review partner and sales opportunity data using Excel, dashboards and AI-assisted tools
• Interview stakeholders and observe system workflows to create process maps, job aids and first drafts
• Support improvements to the partner web portal by documenting needs, testing updates and tracking open items with Sales Operations and GF IT
• Research potential partners and summarize findings for team discussions and decisions
• Prepare insights, presentations and summaries for sales funnel reviews, partner business reviews and leadership updates
• Create and maintain partner training and communication materials using AI-assisted tools
• Own one well-defined project from start to finish and present results and recommendations at the end of the internship
• Perform activities safely and support Environmental, Health, Safety & Security requirements and programs

Commercial Excellence Intern, Partner Excellence

Application Engineer

• Provide technical support to customers and align GlobalFoundries technology offerings with targeted application and market needs
• Engage with customers to understand technical needs for semiconductor IC product development
• Learn GlobalFoundries technology offerings by engaging with internal experts and exploring key features and differentiators
• Collaborate with internal teams, account managers, product marketing, and technical experts to create application-specific technical presentations and proposals
• Support customers through technical evaluations, design-in activities, and tapeout processes with GF subject matter experts
• Develop customer-facing technical documentation demonstrating how GF technologies address application and market challenges
• Identify and resolve technical issues affecting design-win conversion, tapeout readiness, or customer adoption
• Perform activities safely and responsibly and support Environmental, Health, Safety & Security requirements and programs

Field Application Engineer, New College Graduate

• Provide technical support to customers
• Collaborate on new opportunities
• Support evaluations of GlobalFoundries technologies
• Help drive successful design wins leading to tapeouts and first-time-right silicon outcomes
• Build understanding of GlobalFoundries technology offerings by engaging with internal experts
• Collaborate with cross-functional teams to align GF technologies with customer needs and application requirements
• Support customers through technical evaluations and tapeout processes with GF subject matter experts
• Develop customer-facing technical documentation addressing application and market challenges
• Perform activities safely and responsibly
• Support Environmental, Health, Safety & Security requirements and programs

Field Application Engineering Intern – Summer 2027

Electrical Engineer

• Understand key GlobalFoundries technology offerings
• Review customer product portfolios and engage with subject matter experts to analyze technology fit
• Review customer and competitor press releases, earnings calls, and financial statements
• Present competitive analysis
• Read market reports and perform market analysis
• Assist with daily business processes and long-range planning
• Support Account Managers with business initiatives and customer-facing analysis
• Participate in business reviews, sales meetings, strategy meetings, and supply meetings
• Perform activities safely and responsibly
• Support Environmental, Health, Safety & Security requirements and programs

Sales Account Manager Intern, Electrical Engineering – Business

• Engage with customers to understand their technical needs for semiconductor integrated-circuit products
• Assess the competitive landscape and advocate winning GF value propositions
• Partner with account managers, product marketing, and technical experts to create application-specific presentations
• Work with account management to combine technical and commercial terms into design-winning proposals
• Identify and resolve issues or concerns to convert design wins into product tapeouts
• Advocate internally for improved features and capabilities where competitive gaps exist
• Perform all activities safely and responsibly
• Support Environmental, Health, Safety & Security requirements and programs

• Familiarize with GF technology offerings and learn technology features and differentiation from GF experts
• Collaborate with internal teams and stakeholders to match GF technology offerings with customer requirements
• Assist customers with technical evaluation and tapeout execution in partnership with GF subject matter experts
• Create customer-facing technical documentation demonstrating how GF technology solves application and market needs
• Perform all activities safely and responsibly
• Support Environmental, Health, Safety & Security requirements and programs

Field Application Engineering Intern, Summer 2027

Mechanical Engineer

• Design and develop digital CMOS circuits, digital subsystems, and reusable IP for advanced semiconductor applications
• Own digital IC development from microarchitecture and RTL implementation through functional verification, synthesis, timing closure, physical implementation, tapeout, and silicon validation
• Develop and execute verification strategies using simulation, assertions, coverage, and regression methodologies
• Perform and support synthesis, static timing analysis, clock/reset design, power analysis, design-for-test, physical implementation, post-layout verification, and design signoff
• Optimize digital architectures for power, performance, area, reliability, and operating-temperature requirements, including cryogenic conditions
• Collaborate with PDK, device modeling, technology, analog, layout, and EDA teams
• Define silicon test and characterization requirements, analyze measured data, debug digital functionality and timing issues, and correlate silicon behavior with pre-silicon models
• Lead technical design reviews, document design methodology and results, mentor engineers, and collaborate with internal and external teams
• Perform activities safely and support Environmental, Health, Safety & Security requirements and programs

CryoCMOS Digital IC Design Engineer – Quantum

Solutions Engineer

• Lead development of semiconductor integration architectures supporting quantum computing platforms
• Define integration strategies spanning front-end devices, BEOL routing, photonic interfaces, advanced packaging, interconnect technologies, and quantum-specific process modules
• Develop and maintain technology roadmaps supporting long-term scalability, manufacturability, and qualification of quantum hardware
• Identify critical technology gaps and drive closure plans through internal development and external collaborations
• Lead definition and execution of integrated process flows, module interactions, process windows, and technology learning cycles
• Drive integration optimization using DOE methodologies, statistical analysis, and yield learning techniques
• Establish integration checkpoints, performance metrics, and technical success criteria
• Evaluate technology tradeoffs involving performance, manufacturability, reliability, yield, cost, and scalability
• Collaborate with device engineering, process module teams, manufacturing, reliability, modeling, design enablement, and packaging organizations
• Translate quantum system requirements into actionable semiconductor technology requirements and development plans
• Support customer and partner engagements through technical presentations, roadmap discussions, and program reviews
• Contribute to externally funded programs, strategic partnerships, and joint development agreements
• Analyze electrical, physical, reliability, and metrology data to identify integration challenges and improvement opportunities
• Lead root-cause investigations and corrective action planning for integration-related issues
• Develop predictive models and learning frameworks that accelerate technology maturation
• Mentor junior engineers and MTS-level contributors
• Provide technical guidance across integration disciplines
• Influence organizational technical direction through expert knowledge and demonstrated execution
• Contribute to invention disclosures, publications, patents, and technology strategy planning
• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs

Quantum Ion Trap Integration Engineer

• Design and develop high-performance analog and mixed-signal CMOS circuits and reusable IP, including amplifiers, bias and reference circuits, regulators, data converters, oscillators, PLLs, clocking circuits, and drivers
• Own circuit development from architecture and transistor-level design through simulation, layout supervision, physical verification, tapeout, silicon characterization, and design-to-measurement correlation
• Perform circuit analysis across process, voltage, and temperature, including Monte Carlo/mismatch, noise, stability, linearity, timing, and post-layout parasitic simulations
• Optimize circuit performance across operating temperature ranges, including cryogenic conditions, power constraints, process variation, device behavior, and layout-dependent effects
• Collaborate with device modeling and PDK teams on model accuracy, model or design-rule gaps, and cryogenic and advanced PDK development and validation
• Drive analog layout requirements and reviews for matching, common-centroid structures, shielding, isolation, parasitic management, signal integrity, power integrity, and design for manufacturability
• Define silicon test structures and characterization plans, analyze measured data, debug performance issues, and correlate hardware results with pre-silicon simulation and compact models
• Lead technical design reviews, document design methodology and results, mentor engineers, and collaborate with internal and external cross-functional teams
• Perform activities safely and support Environmental, Health, Safety & Security requirements and programs

Cryo CMOS Analog Design Engineer

Architect

• Define and maintain the overall architecture for all Quantum PDKs (QPDKs)
• Create QPDKs from existing GF PDKs, balancing reuse, customization, and maintainability
• Drive a LEAN PDK philosophy by eliminating unnecessary legacy content, tools, layers, devices, and processes
• Own QPDK version control infrastructure, release baselines, branching strategies, access control, and configuration management
• Define and improve QPDK development, quality assurance, release, and change-management processes
• Drive timely, high-quality QPDK releases through governance, planning, and execution
• Evaluate source PDK updates and selectively integrate enhancements
• Leverage AI, automation, and data-driven methodologies to improve efficiency, quality, and time-to-market
• Assess, define, and drive Assembly Design Kit (ADK) requirements and integration strategies with the 3DIC internal team
• Manage licensing, compute resources, and development environments
• Provide technical leadership, mentoring, and architectural reviews
• Maintain expertise in a core PDK discipline and contribute directly to development
• Support Environmental, Health, Safety & Security requirements and programs

Quantum Cryo PDK Architect

General

• Gain hands-on experience evaluating internal controls, understanding business processes, and supporting audit activities
• Assist with business-process walkthroughs
• Document key controls
• Support testing of control design and operating effectiveness under Internal Audit team guidance
• Gather, sample, and analyze data to support audit conclusions
• Evaluate compliance with company policies, procedures, and applicable requirements
• Prepare audit workpapers
• Summarize testing results and observations
• Maintain organized documentation supporting audit findings and recommendations
• Collaborate with Internal Audit team members and cross-functional partners
• Clarify process details and support audit activities
• Participate in team meetings, training, and professional development
• Perform activities safely and responsibly
• Support Environmental, Health, Safety & Security requirements and programs

Internal Audit Intern, Summer 2027

• Design and develop RF and microwave integrated circuits and reusable IP for cryogenic CMOS, quantum systems, and advanced semiconductor applications
• Own RFIC development from architecture and transistor-level design through schematic simulation, electromagnetic-aware layout, physical verification, tapeout, and silicon characterization
• Perform RF circuit analysis across process, voltage, and temperature, including S-parameters, noise figure, gain, linearity, stability, phase noise, power, impedance matching, and post-layout parasitic effects
• Perform or drive electromagnetic simulation and modeling of RF passive structures, interconnects, transmission lines, inductors, transformers, matching networks, and critical layout structures
• Optimize RF circuit performance for power, bandwidth, noise, linearity, area, process variation, package/interconnect parasitics, and operating temperature
• Collaborate with device modeling, PDK, technology, packaging, and test teams to improve RF and cryogenic design enablement
• Define RF silicon test structures and characterization plans, analyze measured data, debug performance issues, and correlate hardware results with circuit and electromagnetic simulations
• Lead technical design reviews, document design methodology and results, mentor engineers, and collaborate with internal and external teams
• Perform activities safely and support Environmental, Health, Safety & Security requirements and programs

Cryo RFIC Design Engineer – Quantum

• Design and develop high-performance analog and mixed-signal CMOS circuits and reusable IP
• Own circuit development from architecture and transistor-level design through simulation, layout supervision, physical verification, tapeout, silicon characterization, and design-to-measurement correlation
• Perform circuit analysis across process, voltage, and temperature, including Monte Carlo/mismatch, noise, stability, linearity, timing, and post-layout parasitic simulations
• Optimize circuit performance across operating temperature ranges, including cryogenic conditions, power constraints, process variation, device behavior, and layout-dependent effects
• Collaborate with device modeling and PDK teams on model accuracy, design-rule gaps, and cryogenic and advanced PDK development
• Drive analog layout requirements and reviews for matching, shielding, isolation, parasitic management, signal integrity, power integrity, and manufacturability
• Define silicon test structures and characterization plans, analyze measured data, debug performance issues, and correlate hardware results with pre-silicon simulation and compact models
• Lead technical design reviews, document design methodology and results, mentor engineers, and collaborate with internal and external teams
• Perform activities safely and support Environmental, Health, Safety & Security requirements and programs

Quantum Analog IC Design Engineer

• Design and develop digital CMOS circuits, digital subsystems, and reusable IP for advanced semiconductor applications
• Own digital IC development from microarchitecture and RTL implementation through functional verification, synthesis, timing closure, physical implementation, tapeout, and silicon validation
• Develop and execute verification strategies using simulation, assertions, coverage, and regression methodologies
• Perform and support synthesis, static timing analysis, clock/reset design, power analysis, design-for-test, physical implementation, post-layout verification, and design signoff
• Optimize digital architectures for power, performance, area, reliability, and operating-temperature requirements, including cryogenic operating conditions
• Collaborate with PDK, device modeling, technology, analog, layout, and EDA teams
• Define silicon test and characterization requirements, analyze measured data, debug digital functionality and timing issues, and correlate silicon behavior with pre-silicon models and simulations
• Lead technical design reviews, document design methodology and results, mentor engineers, and collaborate with cross-functional internal and external teams
• Perform all activities in a safe and responsible manner and support Environmental, Health, Safety & Security requirements and programs

Business Analyst – New College Graduate

Commercial Excellence Intern, Partner Excellence

Field Application Engineer, New College Graduate

Field Application Engineering Intern – Summer 2027

Sales Account Manager Intern, Electrical Engineering – Business

Field Application Engineer, New College Graduate

Field Application Engineering Intern, Summer 2027

CryoCMOS Digital IC Design Engineer – Quantum

Quantum Ion Trap Integration Engineer

Cryo CMOS Analog Design Engineer

Quantum Cryo PDK Architect

Internal Audit Intern, Summer 2027

Cryo RFIC Design Engineer – Quantum

Quantum Analog IC Design Engineer

CryoCMOS Digital IC Design Engineer, Quantum