CPU IP Design & Verification Intern – RISC-V Processor Development

GlobalFoundries

. Support RISC-V CPU microarchitecture and SystemVerilog RTL design and development .

Posted 10/23/2026internshipUnited StatesEntry Level💰 $20 - $40 per hourWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in RISC-V CPU microarchitecture and SystemVerilog RTL design, with strong programming skills in Python and C/C++. Capable of conducting thorough verification and debugging processes while adhering to safety and environmental standards.

Highest-signal resume keywords

RISC-V CPU MicroarchitectureSystemVerilog RTL DesignPython ProgrammingCPU Verification and DebuggingDigital Logic Design

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SystemVerilogC/C++ ProgrammingDigital Logic DesignCPU FundamentalsVerification TestsAssertionsFunctional CoverageSimulationDebuggingAssembly Language Programming

Soft Skills

Analytical SkillsProblem-Solving SkillsCommunication Skills

Tools & Technologies

GitLinuxUVMWaveform Debug

Industry Keywords

CPU ArchitectureMicroarchitectureFPGAASICMemory HierarchyInstruction Set ArchitectureEnvironmental Health Safety

Tech Stack

Tools & technologies

AssemblyLinuxPythonC++

About the role

Key responsibilities & impact

Support RISC-V CPU microarchitecture and SystemVerilog RTL design and development
Contribute to CPU functions including instruction fetch and decode, execution, load/store, caches and memory interfaces, control and status registers, exceptions, and interrupts
Develop verification tests, assertions, checkers, and functional coverage for CPU features
Run CPU simulations and regressions and debug failures using logs, architectural traces, and waveforms
Verify processor functionality across instructions, privilege modes, memory operations, and architectural corner cases
Support CPU power, performance, and area analysis and optimization
Develop Python, C/C++, or scripting-based automation to improve design, verification, regression, and debug productivity
Document technical results and communicate findings to the engineering team
Perform activities safely and responsibly and support Environmental, Health, Safety & Security requirements and programs

Requirements

What you’ll need

At least a sophomore at time of application and actively pursuing a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field through an accredited degree program during the internship
Overall GPA of at least 3.0 and good academic standing
English fluency (written and verbal)
Ability to work at least 40 hours per week during the internship
Coursework or project experience in digital logic design and computer architecture
Familiarity with Verilog or SystemVerilog
Understanding of CPU fundamentals including pipelines, instruction execution, loads/stores, caches, and memory hierarchy
Programming or scripting experience with Python, C/C++, or similar languages
Strong analytical, problem-solving, and debugging skills
Prior related internship or co-op experience (preferred)
Knowledge of the RISC-V Instruction Set Architecture (ISA) (preferred)
Experience with SystemVerilog/UVM, assertions, functional coverage, or constrained-random verification (preferred)
CPU architecture, microarchitecture, FPGA, ASIC, or processor-design project experience (preferred)
Familiarity with caches, memory subsystems, privilege modes, exceptions, interrupts, or virtual memory (preferred)
Experience with simulation, waveform debug, Git, and Linux (preferred)
Exposure to synthesis, lint, clock-domain crossing analysis, formal verification, or timing analysis (preferred)
Assembly-language programming experience (preferred)

Benefits

Comp & perks

One-on-one mentorship
Work assignments prioritizing growth and potential
Professional development opportunities
Networking opportunities with executives