Cryo CMOS Analog Design Engineer

GlobalFoundries

. Design and develop high-performance analog and mixed-signal CMOS circuits and reusable IP, including amplifiers, bias and reference circuits, regulators, data converters, oscillators, PLLs, clocking circuits, and drivers .

Posted 9/28/2026full-timeUnited StatesMid-LevelSenior💰 $118,000 - $275,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in designing and developing high-performance analog and mixed-signal CMOS circuits, with a strong focus on circuit analysis, optimization, and silicon validation. Proven ability to lead design reviews, mentor engineers, and collaborate effectively across teams.

Highest-signal resume keywords

Analog Circuit DesignCMOS Design FundamentalsSPICE SimulationSilicon ValidationCircuit Performance Analysis

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Analog Circuit DesignMixed-Signal DesignCMOS TechnologyCircuit SimulationLayout SupervisionPhysical VerificationParasitic ExtractionMonte Carlo AnalysisDevice PhysicsDesign for Manufacturability

Soft Skills

CollaborationMentoringTechnical LeadershipProblem SolvingCommunication

Tools & Technologies

SPICEDRC/LVS ToolsPost-Layout Extraction EnvironmentsPDK DevelopmentSilicon Test Structures

Industry Keywords

Analog IC DesignMixed-Signal CircuitsSilicon CharacterizationEnvironmental Health SafetyCryogenic Conditions

About the role

Key responsibilities & impact

Design and develop high-performance analog and mixed-signal CMOS circuits and reusable IP, including amplifiers, bias and reference circuits, regulators, data converters, oscillators, PLLs, clocking circuits, and drivers
Own circuit development from architecture and transistor-level design through simulation, layout supervision, physical verification, tapeout, silicon characterization, and design-to-measurement correlation
Perform circuit analysis across process, voltage, and temperature, including Monte Carlo/mismatch, noise, stability, linearity, timing, and post-layout parasitic simulations
Optimize circuit performance across operating temperature ranges, including cryogenic conditions, power constraints, process variation, device behavior, and layout-dependent effects
Collaborate with device modeling and PDK teams on model accuracy, model or design-rule gaps, and cryogenic and advanced PDK development and validation
Drive analog layout requirements and reviews for matching, common-centroid structures, shielding, isolation, parasitic management, signal integrity, power integrity, and design for manufacturability
Define silicon test structures and characterization plans, analyze measured data, debug performance issues, and correlate hardware results with pre-silicon simulation and compact models
Lead technical design reviews, document design methodology and results, mentor engineers, and collaborate with internal and external cross-functional teams
Perform activities safely and support Environmental, Health, Safety & Security requirements and programs

Requirements

What you’ll need

Bachelor’s degree in Electrical Engineering, Microelectronics, Computer Engineering, Applied Physics, or a related field
Minimum 5 years of relevant analog or mixed-signal integrated circuit design experience
Demonstrated experience taking analog or mixed-signal circuits through schematic design, simulation, layout, DRC/LVS, parasitic extraction, tapeout, and silicon validation
Strong knowledge of CMOS analog design fundamentals, including device physics, noise, matching, feedback, stability, frequency response, process variation, and PVT/Monte Carlo analysis
Proficiency with industry-standard analog IC design, SPICE simulation, layout, physical verification, and post-layout extraction environments
Ability to independently analyze complex circuit and silicon performance issues and translate results into design improvements
Up to 10% travel
Fluency in English, written and verbal