CryoCMOS Digital IC Design Engineer, Quantum

GlobalFoundries

. Design and develop digital CMOS circuits, digital subsystems, and reusable IP for advanced semiconductor applications .

Posted 9/28/2026full-timeUnited StatesMid-LevelSenior💰 $98,000 - $202,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Expertise in digital CMOS circuit design and development, including RTL implementation, functional verification, and timing closure. Proficient in debugging complex digital functionality and timing issues while collaborating with cross-functional teams to optimize designs for performance and reliability.

Highest-signal resume keywords

Digital IC DevelopmentRTL Design and VerificationSynthesis and Static Timing AnalysisLow-Power Design ConceptsFluency in English Language

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

Digital CMOS CircuitsRTL ImplementationVerilogSystemVerilogVHDLSynthesisStatic Timing AnalysisDesign-for-TestPhysical ImplementationDebugging

Soft Skills

CollaborationMentoringTechnical Design Reviews

Tools & Technologies

EDA ToolsSimulation ToolsCoverage MethodologiesRegression Methodologies

Industry Keywords

ASIC DesignDigital DesignPower AnalysisCryogenic Operating ConditionsEnvironmental Health Safety

About the role

Key responsibilities & impact

Design and develop digital CMOS circuits, digital subsystems, and reusable IP for advanced semiconductor applications
Own digital IC development from microarchitecture and RTL implementation through functional verification, synthesis, timing closure, physical implementation, tapeout, and silicon validation
Develop and execute verification strategies using simulation, assertions, coverage, and regression methodologies
Perform and support synthesis, static timing analysis, clock/reset design, power analysis, design-for-test, physical implementation, post-layout verification, and design signoff
Optimize digital architectures for power, performance, area, reliability, and operating-temperature requirements, including cryogenic operating conditions
Collaborate with PDK, device modeling, technology, analog, layout, and EDA teams
Define silicon test and characterization requirements, analyze measured data, debug digital functionality and timing issues, and correlate silicon behavior with pre-silicon models and simulations
Lead technical design reviews, document design methodology and results, mentor engineers, and collaborate with cross-functional internal and external teams
Perform all activities in a safe and responsible manner and support Environmental, Health, Safety & Security requirements and programs

Requirements

What you’ll need

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Microelectronics, or a related field
Minimum 5 years of relevant digital integrated circuit or ASIC design experience
Demonstrated experience with RTL design and verification using Verilog, SystemVerilog, VHDL, or equivalent hardware-description languages
Experience with ASIC design flows including synthesis, static timing analysis, clock/reset methodology, design-for-test, physical implementation, timing closure, and signoff
Strong understanding of synchronous digital design, clock-domain crossing, reset-domain crossing, low-power design concepts, and PVT-related timing behavior
Proficiency with industry-standard digital design, verification, implementation, and analysis tools
Ability to independently debug complex pre-silicon and silicon issues
Up to 10% travel
Fluency in English Language - written & verbal