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GlobalFoundries

Director, Design Engineering

GlobalFoundries

. Lead the design and execution of complex SoC, AI/ML, networking, compute, or edge-processing products .

Posted 10/26/2026full-timeAustin • Texas • United StatesLead💰 $191,000 - $332,000 per yearWebsite

Core Competencies

Role fit
Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates extensive expertise in leading complex SoC and AI/ML product designs, with a strong focus on front-end development, design methodologies, and team leadership. Proven ability to align technical execution with business objectives while fostering collaboration across multiple disciplines.

Highest-signal resume keywords
SoC Design LeadershipFront-End Design ExpertiseEngineering Management ExperienceAdvanced Technology Node ExperienceCustomer-Facing Communication Skills

ATS Keywords

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Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills
RTL DesignMicroarchitecture DevelopmentSynthesisTiming ClosureDesign VerificationDFT MethodologiesCDC/LintRTL-to-GDSII DevelopmentLow-Power Design MethodologiesChiplet Integration
Soft Skills
Team LeadershipMentoringExecutive CommunicationCollaborationRisk Assessment
Tools & Technologies
EDA ToolsAI FlowsAgile MethodologiesAdvanced Packaging TechnologiesSilicon Learning
Industry Keywords
Semiconductor DesignASIC Tape-OutAI/ML AcceleratorsNetworking ProductsHigh-Performance ComputingFoundry PartnershipsTechnology Roadmap DevelopmentEnvironmental Health Safety & Security

About the role

Key responsibilities & impact
  • Lead the design and execution of complex SoC, AI/ML, networking, compute, or edge-processing products
  • Drive front-end development from architecture definition through RTL implementation, integration, synthesis, timing closure, and tape-out readiness
  • Establish and enforce design methodologies, design quality metrics, and execution frameworks
  • Use modern AI flows and agile methodologies for fast design development
  • Guide technical decisions involving performance, power, area, reliability, manufacturability, and product cost
  • Partner with architecture teams to evaluate product concepts and technology feasibility
  • Build, mentor, and lead high-performing design teams across multiple disciplines and geographies
  • Develop organizational capabilities spanning architecture, RTL, integration, verification, DFT, physical design, and silicon bring-up
  • Drive talent acquisition, succession planning, and leadership development
  • Collaborate with Architecture, Verification, DFT, Physical Design, Package Design, Software, Product Engineering, Foundry, and Operations teams
  • Interface with customers, ecosystem partners, IP providers, EDA vendors, and technology partners
  • Align technical execution with business objectives, schedules, and product roadmaps
  • Lead reviews, executive communications, risk assessments, and program status reporting
  • Define and execute design strategies for advanced semiconductor technologies
  • Partner with foundries and ecosystem partners on technology enablement, PDK readiness, IP qualification, and silicon learning
  • Drive adoption of advanced design methodologies, low-power architectures, chiplet integration, 2.5D/3D packaging, and emerging AI-driven design flows
  • Perform all activities in a safe and responsible manner and support Environmental, Health, Safety & Security requirements and programs

Requirements

What you’ll need
  • Bachelor's, Master's, or Ph.D. in Electrical Engineering, Computer Engineering, or related field
  • 15+ years of semiconductor design experience with progressive technical and leadership responsibility
  • 8+ years of engineering management experience, including leadership of senior technical teams
  • Proven track record of delivering multiple successful ASIC/SoC tape-outs across advanced technology nodes
  • Strong hands-on expertise in front-end design, including RTL design and integration, microarchitecture development, synthesis, CDC/Lint, DFT and test methodologies, timing closure, and design verification collaboration
  • Deep understanding of complete RTL-to-GDSII development flows
  • Demonstrated experience working on large-scale, complex SoC designs involving multiple IPs, subsystems, and cross-functional teams
  • Strong customer-facing and executive communication skills
  • Experience with advanced technology nodes, AI/ML accelerators, compute platforms, networking, automotive, or high-performance computing products, advanced packaging technologies, leading foundries and ecosystem partners, low-power design methodologies, customer engagements, strategic partnerships, and technology roadmap development are preferred