Senior Principal Engineer – AI/ML

GlobalFoundries

. Drive the micro-architecture and design of critical blocks of the CPU core .

Posted 9/18/2026full-timeSanta Clara • California • United StatesSenior💰 $171,000 - $325,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in CPU microarchitecture design, including RISC-V Vector CPU core development and AI-enabled Matrix engine integration. Proficient in RTL design, functional verification, and high-performance CPU strategies, with a strong focus on power, performance, and area optimization.

Highest-signal resume keywords

RISC-V Vector CPU Core DesignMicroprocessor Architecture ExpertiseSystem Verilog, Verilog, VHDL KnowledgeFunctional Verification SupportHigh-Performance CPU Techniques

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Microarchitecture DevelopmentPipeline Stages KnowledgeCache Coherency UnderstandingHardware Multi-Threading ExperienceScripting Language Proficiency

Tools & Technologies

SimulatorsWaveform Debugging Tools

Certifications & Qualifications

Master’s DegreePhD

Industry Keywords

CPU Core DesignAI-Enabled Matrix EngineLow-Power Microarchitecture TechniquesCPU Integration at SoC LevelSafety and Security Microarchitecture

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Drive the micro-architecture and design of critical blocks of the CPU core
Design of RISC-V Vector CPU core and its custom extensions
Design of AI-enabled Matrix engine to augment the Vector CPU
Explore high-performance strategies working with the CPU modeling team
Perform microarchitecture development and specification from early high-level architectural exploration through microarchitectural research to detailed specifications
Configure design features development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
Perform functional verification support and assist in the design verification strategy
Assist with verification of RTL design performance goals
Partner with a multifunctional engineering team to implement and validate physical design aspects of timing, area, reliability, testability, and power
Perform all activities in a safe and responsible manner and support Environmental, Health, Safety & Security requirements and programs

Requirements

What you’ll need

Hands-on working knowledge of the pipeline stages of an in-order or out-of-order high-performance CPU core
Thorough knowledge of microprocessor architecture, including expertise in one or more of: instruction fetch and decode, branch prediction techniques, instruction scheduling, register renaming, Reorder Buffer (ROB), out-of-order execution, integer and floating-point execution, load/store execution, instruction and data prefetch, vector data path, cache and memory subsystems
Knowledge of cache coherency and memory consistency
Knowledge of System Verilog, Verilog and/or VHDL
Experience with simulators and waveform debugging tools
Knowledge of logic design principles along with timing and power implications
Master’s with 10+ years of experience, or PhD with 5+ years of work experience
Experience with designing RISC-V, ARM, and/or MIPS CPU
Experience with hardware multi-threading, virtualization, and SIMD designs
Experience with vector and matrix-enabled CPUs, preferably RISC-V processors
Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
Understanding of low-power microarchitecture techniques
Experience using a scripting language such as Perl or Python
Understanding of CPU integration at SoC level
Understanding of Safety and Security microarchitecture