Testsite Engineer, Quantum

GlobalFoundries

. Design and develop in-house test chips, testsites, and test structures to characterize semiconductor technologies and improve understanding of customer design and technology requirements .

Posted 9/25/2026full-timeEssex Junction • New York • United StatesMid-LevelSenior💰 $98,000 - $176,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in semiconductor IC design, electrical characterization, and data analysis, with a strong ability to translate technical findings into actionable improvements. Proficient in collaborating across multidisciplinary teams to optimize test chip designs and ensure alignment with technology requirements.

Highest-signal resume keywords

Semiconductor IC DesignElectrical CharacterizationData AnalysisDesign Verification FlowsProject Management

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Electrical MeasurementDevice CharacterizationSchematic CaptureLayout DesignDRC/LVSSimulationDesign-to-Mask ReleaseSilicon Measurement Data InterpretationTest Chip DesignTechnology Development

Soft Skills

Written CommunicationVerbal CommunicationPlanningOrganizational Skills

Tools & Technologies

EDA EnvironmentsData-Analysis Tools

Industry Keywords

CMOS Process TechnologyDevice PhysicsProcess VariationReliabilityDesign-Technology Interaction

About the role

Key responsibilities & impact

Design and develop in-house test chips, testsites, and test structures to characterize semiconductor technologies and improve understanding of customer design and technology requirements
Define and implement chip-level and device-level structures for electrical measurement, technology characterization, and development learning
Collaborate with technology development, design enablement, product, test, and manufacturing teams to translate characterization needs into testsite requirements and silicon implementations
Evaluate and process internal and customer designs through design-to-mask readiness, including layout review and applicable design-rule, verification, and release activities
Plan and execute electrical characterization and other relevant testing of fabricated test chips
Analyze silicon data, identify trends and performance gaps, and translate results into recommendations for technology, model, design-rule, or testsite optimization
Iterate testsite and chip designs based on measured silicon results
Document testsite architecture, design intent, measurement results, and technical conclusions, and communicate findings to cross-functional stakeholders
Perform activities safely and support Environmental, Health, Safety & Security requirements and programs
Work collaboratively on other projects and assignments as needed

Requirements

What you’ll need

Bachelor’s degree in Electrical Engineering, Computer Engineering, Applied Physics, Microelectronics, or a related technical field
Relevant experience in semiconductor IC or test-chip design, technology development, device characterization, product engineering, or a related field; minimum years of experience to be aligned with the applicable GF career level and scoping guidelines
Working knowledge of semiconductor devices, integrated-circuit design or layout, electrical characterization, and interpretation of silicon measurement data
Experience with semiconductor design and verification flows such as schematic capture, layout, DRC/LVS, extraction, simulation, or design-to-mask release processes
Ability to analyze technical data, identify root causes and trends, and translate results into design or technology improvements
Fluency in English, written and verbal
Preferred: Master’s degree or PhD in Electrical Engineering, Computer Engineering, Applied Physics, Microelectronics, or a related field
Preferred experience designing semiconductor test chips, process-control or characterization structures, or dedicated technology-development testsites
Preferred experience with industry-standard EDA environments and data-analysis tools used for IC design, verification, characterization, and silicon debug
Preferred understanding of CMOS process technology, device physics, parasitic effects, process variation, reliability, and design-technology interaction
Preferred experience working across design, process integration, characterization, modeling, PDK, test, or manufacturing organizations
Preferred project management, written and verbal communication, planning, and organizational skills