Senior ASIC Physical Design Engineer

Hewlett Packard Enterprise

. Support development of complex, high-performance integrated circuits .

Posted 10/9/2026full-timeUnited StatesSenior💰 $147,000 - $279,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in ASIC and VLSI design implementation, with a strong focus on timing analysis, synthesis, and physical design. Proficient in using industry-standard EDA tools and scripting for flow automation to enhance design quality and efficiency.

Highest-signal resume keywords

ASIC Design ImplementationStatic Timing AnalysisSynthesis and Netlist Quality AnalysisEDA Tools ProficiencyDigital Logic and Circuit Design

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Timing ClosureTiming ConstraintsFormal VerificationChip PartitioningFloorplanningECO ImplementationDigital LogicCircuit DesignComputer ArchitectureVLSI Principles

Soft Skills

Analytical SkillsProblem-Solving SkillsDebugging SkillsEffective CommunicationCollaboration Skills

Tools & Technologies

Synopsys Fusion CompilerDesign CompilerPrimeTimeFormalityCadence RTL CompilerGenusLECPerlPythonTcl

Industry Keywords

Integrated CircuitsPhysical DesignTiming AnalysisDesign QualityEngineering Change OrdersCross-Functional TeamsContinuous ImprovementHierarchical DesignsTiming BudgetsCompliance Standards

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Support development of complex, high-performance integrated circuits
Contribute to design quality, synthesis, formal verification, partitioning, floorplanning, timing analysis, timing closure, and signoff activities
Perform static timing analysis for hierarchical designs at partition and full-chip levels
Create, validate, and maintain timing constraints and timing budgets
Drive timing closure for partition-level and full-chip designs, including setup, hold, clock, I/O, and test timing
Analyze timing reports, identify critical paths, and implement fixes for performance, power, and area objectives
Perform synthesis, netlist quality checks, and formal verification
Support chip partitioning, floorplanning, and physical design implementation
Create and manage functional engineering change orders (ECOs)
Develop flow automation and methodology improvements
Partner with cross-functional engineering teams on physical-design-aware architecture and implementation
Review activities for compliance with ASIC technology, methodology, and development standards
Provide technical guidance and mentoring to less-experienced engineers
Contribute to continuous improvement across the design organization

Requirements

What you’ll need

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, Microelectronics, or a related technical field
Typically 6–10 years of experience in ASIC, VLSI, or semiconductor design implementation, including physical design and timing closure
Strong understanding of digital logic, circuit design, computer architecture, VLSI principles, and ASIC physical design
Experience with static timing analysis and timing signoff
Experience with timing constraints and validation
Experience with synthesis and netlist quality analysis
Experience with formal verification
Experience with floorplanning and chip partitioning
Experience with ECO implementation
Experience with industry-standard EDA tools such as Synopsys Fusion Compiler, Design Compiler, PrimeTime, Formality, Cadence RTL Compiler, Genus, or LEC
Proficiency in scripting and flow automation using Perl, Python, Tcl, or similar languages
Strong analytical, problem-solving, and debugging skills
Effective written and verbal communication skills in English
Ability to work independently and collaboratively across multiple engineering disciplines

Benefits

Comp & perks

Comprehensive benefits supporting physical, financial, and emotional wellbeing
Personal and professional development programs
Flexible work arrangements to manage work and personal needs
Inclusive workplace culture
Reasonable accommodation during the application or interview process for applicants with disabilities
Variable incentives may also be offered