Senior ASIC Physical Design Engineer

Hewlett Packard Enterprise

. Support development of complex, high-performance integrated circuits .

Posted 10/9/2026full-timeUnited StatesSenior💰 $147,000 - $279,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in ASIC and VLSI design implementation, with a strong focus on timing analysis, synthesis, and physical design. Proficient in collaborating across engineering disciplines while providing technical guidance and mentoring to enhance design quality and efficiency.

Highest-signal resume keywords

ASIC Design ImplementationStatic Timing AnalysisSynthesis and Netlist Quality AnalysisDigital Logic and Circuit DesignEDA Tools Proficiency

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Static Timing AnalysisSynthesisFormal VerificationTiming Constraints ValidationChip PartitioningFloorplanningECO ImplementationDigital LogicCircuit DesignVLSI Principles

Soft Skills

Analytical SkillsProblem-SolvingDebugging SkillsEffective CommunicationCollaboration

Tools & Technologies

Synopsys Fusion CompilerDesign CompilerPrimeTimeFormalityCadence RTL CompilerGenusLECPerlPythonTcl

Industry Keywords

ASICVLSISemiconductor DesignTiming ClosurePhysical DesignHierarchical Timing AnalysisFull-Chip Timing ClosureDesign MethodologiesAutomationElectronic Design Automation

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Support development of complex, high-performance integrated circuits
Contribute to design quality, synthesis, formal verification, partitioning, floorplanning, timing analysis, timing closure, and signoff activities
Perform static timing analysis for hierarchical designs at partition and full-chip levels
Create, validate, and maintain timing constraints and timing budgets
Drive timing closure for partition-level and full-chip designs, including setup, hold, clock, I/O, and test timing
Analyze timing reports, identify critical paths, and implement fixes for performance, power, and area objectives
Perform synthesis, netlist quality checks, and formal verification
Support chip partitioning, floorplanning, and physical design implementation
Create and manage functional engineering change orders
Develop flow automation and methodology improvements for synthesis, timing analysis, formal verification, physical design, and signoff
Collaborate with ASIC design, physical implementation, DFT, signal integrity, architecture, and other cross-functional teams
Promote physically aware architecture and implementation
Review design and project activities for compliance with ASIC technology, methodology, and development standards
Provide technical guidance and mentoring to less-experienced engineers
Contribute to continuous improvement across the design organization

Requirements

What you’ll need

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, Microelectronics, or a related technical field
Typically 6–10 years of experience in ASIC, VLSI, or semiconductor design implementation, including physical design and timing closure
Strong understanding of digital logic, circuit design, computer architecture, VLSI principles, and ASIC physical design
Experience with static timing analysis and timing signoff
Experience with timing constraints and validation
Experience with synthesis and netlist quality analysis
Experience with formal verification
Experience with floorplanning and chip partitioning
Experience with ECO implementation
Experience with industry-standard EDA tools, such as Synopsys Fusion Compiler, Design Compiler, PrimeTime, Formality, Cadence RTL Compiler, Genus, or LEC
Proficiency in Perl, Python, Tcl, or similar scripting languages
Strong analytical, problem-solving, and debugging skills
Effective written and verbal communication skills in English
Ability to work independently and collaboratively across multiple engineering disciplines
Preferred: experience with hierarchical timing analysis and full-chip timing closure
Preferred: experience with clock, I/O, test, and specialized timing-closure challenges
Preferred: experience developing ASIC implementation flows, automation, and design methodologies
Preferred: experience with advanced process technologies and complex, high-performance ASIC designs
Preferred: demonstrated technical leadership, mentoring, and cross-functional influence
Preferred: graduate coursework or a Master's degree
Preferred: publications, patents, or demonstrated contributions in ASIC, VLSI, physical design, or electronic design automation

Benefits

Comp & perks

Comprehensive benefits supporting physical, financial, and emotional wellbeing
Personal and professional development programs
Career development opportunities
Flexible work and personal needs management
Inclusive workplace culture
Employee benefits information available through HPE's US benefits portal