Senior ASIC Physical Design Engineer

Hewlett Packard Enterprise

. Perform static timing analysis for hierarchical designs at partition and full-chip levels .

Posted 10/9/2026full-timeUnited StatesSenior💰 $147,000 - $279,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in static timing analysis, timing closure, and physical design implementation within ASIC and VLSI environments. Proficient in utilizing industry-standard EDA tools and scripting languages to enhance design methodologies and ensure compliance with engineering standards.

Highest-signal resume keywords

Static Timing AnalysisTiming ClosurePhysical Design ImplementationEDA Tools (Synopsys, Cadence)Scripting (Perl, Python, Tcl)

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

Static Timing AnalysisTiming ConstraintsSynthesisNetlist Quality ChecksFormal VerificationFloorplanningChip PartitioningECO ImplementationDigital Logic DesignVLSI Principles

Soft Skills

Analytical SkillsProblem-SolvingDebugging SkillsWritten CommunicationVerbal Communication

Tools & Technologies

Synopsys Fusion CompilerDesign CompilerPrimeTimeFormalityCadence RTL CompilerGenusLEC

Industry Keywords

ASIC DesignVLSI DesignSemiconductor DesignEngineering Change OrdersPhysical Design Standards

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Perform static timing analysis for hierarchical designs at partition and full-chip levels
Create, validate, and maintain timing constraints and timing budgets
Drive timing closure for partition-level and full-chip designs, including setup, hold, clock, I/O, and test timing
Analyze timing reports, identify critical paths, and implement fixes to meet performance, power, and area objectives
Perform synthesis, netlist quality checks, and formal verification
Support chip partitioning, floorplanning, and physical design implementation
Create and manage functional engineering change orders (ECOs)
Develop flow automation and methodology improvements for synthesis, timing analysis, formal verification, physical design, and signoff
Partner with cross-functional engineering teams on physical-design-aware architecture and implementation
Review design and project activities for compliance with ASIC technology, methodology, and development standards
Provide technical guidance and mentoring to less-experienced engineers
Contribute to continuous improvement across the design organization

Requirements

What you’ll need

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, Microelectronics, or a related technical field
Typically 6–10 years of experience in ASIC, VLSI, or semiconductor design implementation, including physical design and timing closure
Strong understanding of digital logic, circuit design, computer architecture, VLSI principles, and ASIC physical design
Experience with static timing analysis and timing signoff
Experience with timing constraints and validation
Experience with synthesis and netlist quality analysis
Experience with formal verification
Experience with floorplanning and chip partitioning
Experience with ECO implementation
Experience with industry-standard EDA tools such as Synopsys Fusion Compiler, Design Compiler, PrimeTime, Formality, Cadence RTL Compiler, Genus, or LEC
Proficiency in Perl, Python, Tcl, or similar scripting languages
Strong analytical, problem-solving, and debugging skills
Effective written and verbal communication skills in English
Ability to work independently and collaboratively across multiple engineering disciplines

Benefits

Comp & perks

Comprehensive benefits supporting physical, financial, and emotional wellbeing
Personal and professional development programs
Flexible work arrangements to manage work and personal needs
Accommodation support during the application or interview process for qualified applicants with disabilities