Principal ASIC Physical Design Engineer

K2 Space Corporation

. Lead implementation of complex SoCs for next-generation satellite and space systems .

Posted 11/12/2026full-timeRemote • United StatesLead💰 $190,000 - $280,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in ASIC physical design, particularly in RTL-to-GDSII flows, timing closure, and managing physical design teams. Proficient in developing methodologies and collaborating across multiple engineering disciplines to optimize SoC performance for satellite systems.

Highest-signal resume keywords

RTL-To-GDSII Flow ExpertiseTiming Closure ManagementPhysical Design Methodologies DevelopmentExperience With Synopsys, Cadence, Siemens ToolsLeadership In Cross-Functional Collaboration

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

ASIC Physical DesignTiming ClosureIR Drop AnalysisECO ImplementationMulti-Clock SoC DesignMulti-Voltage SoC DesignHierarchical SoC DesignFinFET Process NodesDFT IntegrationSTA Sign-Off

Soft Skills

Excellent CommunicationLeadershipCross-Functional CollaborationMentoringTechnical Leadership

Tools & Technologies

Synopsys ToolsCadence ToolsSiemens ToolsEDA ToolsUPFCPF

Industry Keywords

SoC DesignSatellite CommunicationsPhysical VerificationChip-To-Board IntegrationSpaceflight Systems

About the role

Key responsibilities & impact

Lead implementation of complex SoCs for next-generation satellite and space systems
Own the complete RTL-to-GDSII flow, including synthesis, floorplanning, place & route, CTS, STA, physical verification, and sign-off
Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area
Collaborate with front-end, RTL design, DFT, verification, architecture, packaging, test, and post-silicon teams
Drive timing closure across multiple voltage and process corners using foundry-qualified tools
Partner on package-aware floorplanning, signal/power integrity, and chip-to-board integration
Manage and technically guide external physical design partners and service vendors
Work with EDA vendors to debug and optimize tool flows and evaluate methodologies
Support chip bring-up and debug
Support the product through production and spaceflight
Develop and implement new SoC subsystems for satellite communications and beyond
Contribute to cutting-edge SoCs that will fly in space

Requirements

What you’ll need

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
10+ years of experience in ASIC physical design for high-performance SoCs
End-to-end expertise in RTL-to-GDSII flows using Synopsys, Cadence, or Siemens tools
Hands-on experience with timing closure, IR drop analysis, and ECO implementation
Understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs
Experience with advanced FinFET process nodes
Experience managing or coordinating offshore/outsourced physical design teams or vendors
Familiarity with DFT integration, STA sign-off, and power domain implementation using UPF/CPF
Excellent communication, leadership, and cross-functional collaboration skills
Ability to act as a technical leader and subject-matter expert, teaching, growing, and mentoring team members
Must be a U.S. Person as defined by ITAR or otherwise eligible for a federally issued export control license

Benefits

Comp & perks

Equity in the company
Paid time off
Medical coverage
Dental coverage
Vision coverage
Life insurance
Paid parental leave
Comprehensive benefits package
Other perks