Principal ASIC Synthesis, Timing Engineer

K2 Space Corporation

. Lead implementation of complex SoCs for next-generation satellite and space systems .

Posted 11/12/2026full-timeRemote • United StatesLead💰 $190,000 - $280,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in ASIC design for high-performance SoCs, with a strong focus on RTL-to-GDSII flows, timing closure, and physical design integration. Proven ability to lead cross-functional teams and manage external partners while ensuring compliance with ITAR regulations.

Highest-signal resume keywords

RTL-To-GDSII Flow ExpertiseTiming Closure ManagementPhysical Design Constraints UnderstandingEnd-To-End Formal Verification MethodologyLeadership And Mentoring Skills

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

ASIC DesignRTL DevelopmentTiming ClosureLow Power ImplementationECO ImplementationIR Drop AnalysisFormal VerificationLogic Equivalence Check DebugDFT IntegrationPPA Optimization

Soft Skills

Excellent CommunicationLeadershipCross-Functional Collaboration

Tools & Technologies

Synopsys ToolsCadence ToolsSiemens ToolsEDA ToolsAutomation Scripts

Certifications & Qualifications

B.S. or M.S. in Electrical EngineeringU.S. Person Eligibility for ITAR

Industry Keywords

SoC DevelopmentSatellite CommunicationsRadiation-Hardened ASICsTSMC TapeoutsGate-All-Around Technologies

About the role

Key responsibilities & impact

Lead implementation of complex SoCs for next-generation satellite and space systems
Own constraints development and validation from RTL handoff through synthesis
Own the complete RTL-to-synthesis flow at block and top level
Work with physical design teams to integrate floorplanning information for physical synthesis
Develop and maintain methodologies, scripts, and automation to optimize performance, power, and area
Collaborate with architecture, RTL design, DFT, physical design, front-end, and verification teams
Drive timing closure across multiple voltage and process corners, including foundry-qualified sign-off
Own Lint, CDC, and UPF checks and close issues
Develop an end-to-end formal verification methodology
Manage and technically guide external physical design partners and service vendors
Work with EDA vendors to debug and optimize tool flows and evaluate methodologies
Support chip bring-up and debug with post-silicon and test teams
Support the product through production and spaceflight
Develop and implement SoC subsystems for satellite communications and beyond
Drive schedule convergence, first-pass silicon success, timing closure, PPA optimization, and design integration

Requirements

What you’ll need

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
10+ years of experience in ASIC design for high-performance SoCs
Proven end-to-end expertise in RTL-to-GDSII flows using Synopsys, Cadence, or Siemens tools
Strong hands-on experience with timing closure, IR drop analysis, low power implementation, and ECO implementation
Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs
Experience with advanced FinFET process nodes
Prior experience in design convergence with offshore/outsourced physical design teams or vendors
Ability to resolve formal verification issues
Ability to analyze and fix VCLP issues regarding UPF
Experience with logic equivalence check debug, functional ECO development and implementation, and low power checker validation of UPF
Familiarity with DFT integration and STA sign-off with functional ECO implementation
Excellent communication, leadership, and cross-functional collaboration skills
Ability to act as technical leader and subject-matter expert, teaching, growing, and mentoring others
The hired person must be a U.S. person as defined by ITAR or otherwise eligible for a federally issued export control license
Nice-to-have: exposure to radiation-hardened or space-qualified ASICs; physical design service vendor management or offshore collaboration; TSMC tapeouts; Gate-All-Around technologies; cross-functional geographically distributed teams

Benefits

Comp & perks

Equity in the company
Paid time off
Medical, dental, and vision coverage
Life insurance
Paid parental leave
Many other perks
Reasonable accommodation for applications and interviews