Senior ASIC Physical Design Engineer

K2 Space Corporation

. Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification .

Posted 11/12/2026full-timeRemote • United StatesSenior💰 $170,000 - $250,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in ASIC physical design for complex SoCs, including synthesis, floorplanning, and physical verification. Proficient in timing analysis, power optimization, and collaboration with cross-functional teams to ensure successful project execution.

Highest-signal resume keywords

ASIC Physical DesignSynopsys ICC2/Fusion CompilerCadence InnovusTiming AnalysisPower Optimization

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SynthesisFloorplanningPlace & RouteCTSSTAPhysical VerificationDRC/LVSIR Drop AnalysisEM AnalysisECO Implementation

Soft Skills

CollaborationProblem-SolvingCross-Functional CommunicationAdaptability

Tools & Technologies

Physical Design ToolsAutomation ScriptsDFT ToolsUPF/CPF Power Intent

Industry Keywords

SoC DesignFinFET TechnologiesSatellite CommunicationsSpace SystemsMethodology Development

About the role

Key responsibilities & impact

Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification
Perform timing closure and optimization across multiple corners and modes using industry-standard tools
Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence
Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment
Develop and maintain scripts and automation to improve flow efficiency and consistency
Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis
Assist in chip-level integration, ECOs, and tapeout preparation
Contribute to methodology development, tool evaluation, and flow documentation
Support the product through production and spaceflight
Develop and implement new SoC sub-systems for satellite communications and beyond
Contribute to advanced SoCs for satellite and space systems

Requirements

What you’ll need

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
5–10 years of experience in ASIC physical design for complex SoCs
Hands-on experience with Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent
Strong understanding of timing analysis, power optimization, and physical verification flows
Experience with hierarchical or flat SoC design methodologies
Familiarity with FinFET technologies
Working knowledge of DFT, UPF/CPF power intent, and ECO implementation
Ability to work cross-functionally in fast-paced environments
U.S. person status as defined by ITAR or eligibility for a federally issued export control license

Benefits

Comp & perks

Equity in the company
Paid time off
Medical coverage
Dental coverage
Vision coverage
Life insurance
Paid parental leave
Comprehensive benefits package
Other perks