FPGA Developer – Cryptography, High-Performance Networking

Kryptus SA

. Design and implement 100G/200G packet-processing blocks in RTL: Ethernet/IP/ESP parser, classification, IPsec encapsulation and decapsulation, queues, and arbitration .

Posted 10/23/2026full-timeCampinas • BrazilMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in FPGA design and implementation, including proficiency in SystemVerilog or VHDL, and experience with high-speed interfaces and cryptographic hardware. Strong ability to conduct verification processes and ensure compliance with FIPS 140-3 and Common Criteria certification.

Highest-signal resume keywords

FPGA Design and ImplementationSystemVerilog or VHDL ProficiencyCryptographic Hardware ImplementationFIPS 140-3 Certification ExperienceHigh-Speed Interface Knowledge

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL DesignPacket-Processing BlocksCryptographic CoresReal-Time Signal ProcessingTestbench DevelopmentSimulation Flow ProficiencyVerification and CoverageSchematic ReadingLab Instrument UsageFPGA Digital Signal Processing

Soft Skills

CollaborationCommunicationProblem-Solving

Tools & Technologies

VivadoVivado SimulatorQuestaVerilatorGitVitisPetaLinuxZynq UltraScale+ MPSoC

Certifications & Qualifications

FIPS 140-3 CertificationCommon Criteria Certification

Industry Keywords

EthernetIPsecAES-256-GCMSHA-2Side-Channel VulnerabilitiesARM/MPSoCTEMPEST RequirementsCoherent Optical CommunicationsUVMTcl and Python Scripting

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Design and implement 100G/200G packet-processing blocks in RTL: Ethernet/IP/ESP parser, classification, IPsec encapsulation and decapsulation, queues, and arbitration
Implement and integrate hardware cryptographic cores: high-throughput AES-256-GCM, random-number generators, SHA-2 hashing, Toeplitz families for privacy amplification, and post-quantum ML-KEM accelerators
Address side-channel vulnerabilities and failure modes
Design RED/BLACK domain separation in FPGA and interfaces with ARM/MPSoC processors, including secure bitstream loading, self-tests, and zeroization
Close timing on AMD UltraScale+ devices (VU9P, Zynq UltraScale+)
Integrate 100G MACs, SerDes transceivers, AXI4/AXI-Stream, DMA, and external memory
Implement real-time signal processing for CV-QKD receivers, including phase and frequency recovery, filtering, and parameter estimation, in collaboration with the photonics team
Write testbenches, run simulations, and achieve code and requirements coverage
Generate algorithm-validation vectors (CAVP) and support bench testing
Document architecture, interfaces, and evidence for FIPS 140-3 and Common Criteria certification
Participate in design reviews with evaluators
Work with version control, code review, and continuous integration for RTL, including automated regression testing

Requirements

What you’ll need

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field
Demonstrated experience developing FPGA designs with SystemVerilog or VHDL, from RTL through bitstream, on projects deployed to real hardware
Proficiency with Vivado (synthesis, implementation, analysis and timing closure, and debugging with ILA)
Proficiency with at least one simulation flow: Vivado Simulator, Questa, or Verilator
Experience with high-speed interfaces and buses: AXI, SerDes/GTY, PCIe, or 10G/25G/100G Ethernet
Experience with verification: structured testbenches, coverage, and regression testing
Ability to read schematics and use lab instruments such as oscilloscopes and logic analyzers
Git and collaborative code-review practices
Advanced English proficiency
Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related field (preferred)
Experience implementing cryptography in hardware (AES-GCM, SHA, RNG, PQC) and knowledge of side-channel countermeasures (preferred)
Vitis, Vitis HLS, Vitis Networking P4, or Zynq UltraScale+ MPSoC development with PetaLinux (preferred)
FPGA digital signal processing or experience with coherent optical communications (preferred)
Experience with FIPS 140-3 or Common Criteria certification, or with defense projects and TEMPEST requirements (preferred)
UVM or cocotb; Tcl and Python scripting for flow automation (preferred)

Benefits

Comp & perks

Profit-sharing program (PLR)
Health insurance
Dental insurance
Attractive benefits package, including meal and food allowances and a multi-benefit card
Transportation allowance
TotalPass
Day off—celebrate your day your way
SESC partnership
Extended maternity/paternity leave
Mental health platforms, including therapy
Highly skilled technical team
Low bureaucracy and high impact
Freedom with accountability
Diversity, respect, and creativity valued
Opportunities to grow and contribute to strategic technical decisions
Regular happy hours
Recreation and relaxation space
A variety of food and beverages available every day
Regular feedback
Collaborative, low-bureaucracy environment that encourages creativity and professional growth