Senior HW Engineer – Signal and Power Integrity

Lumai

. Own signal and power integrity across boards and packages .

Posted 10/8/2026full-timeOxford • United KingdomSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in signal and power integrity for high-speed PCB and package designs, with proficiency in simulation tools and measurement techniques. Capable of developing methodologies and guidelines to optimize design performance and ensure compliance with industry standards.

Highest-signal resume keywords

Signal Integrity (SI) AnalysisPower Integrity (PI) DesignEM and Circuit Simulation (Ansys HFSS/SIwave, Keysight ADS, Cadence Sigrity/Clarity)Measurement Correlation (VNAs, TDRs, Oscilloscopes)Scripting (Python, MATLAB)

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Applicant Tracking System Keywords

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Hard Skills

Signal Integrity (SI) AnalysisPower Integrity (PI) DesignTransmission Line TheoryS-ParametersCrosstalk AnalysisDC IR Drop AnalysisIBIS and IBIS-AMI ModelsDecoupling OptimizationHigh-Speed PCB Design56G/112G PAM4 Channels

Tools & Technologies

Ansys HFSSKeysight ADSCadence SigrityTDRsVNAsHigh-Speed Oscilloscopes

Industry Keywords

High-Speed InterfacesPCB MaterialsChannel Compliance MetricsChip-Package-Board AnalysisDecoupling Strategies

Tech Stack

Tools & technologies

PythonRuby on Rails

About the role

Key responsibilities & impact

Own signal and power integrity across boards and packages
Run pre-layout channel studies to set routing topologies, stackups, materials and design constraints for high-speed interfaces
Carry out post-layout SI analysis of critical channels, including insertion and return loss, crosstalk, and eye and COM analysis using IBIS-AMI models
Design and optimise vias, breakouts, connector launches, and transitions into optical engines and co-packaged components
Set PDN impedance targets, design decoupling strategies, and run DC drop and AC PDN analysis for high-current ASIC and FPGA rails
Support package, interposer and board co-simulation with the ASIC team
Correlate simulation with lab measurements using TDRs, VNAs and oscilloscopes, and feed results back into models and design rules
Evaluate and characterise PCB materials, connectors and cable assemblies with suppliers and fabricators
Build SI/PI methodology, model libraries and reusable design guidelines
Sign off critical channels on at least one board by month six and determine when layouts are ready to release

Requirements

What you’ll need

A degree in electronic engineering, physics or a related discipline, plus proven SI/PI experience on high-speed PCB and/or package designs
Proficiency with at least one major EM and circuit simulation suite, such as Ansys HFSS/SIwave, Keysight ADS or Cadence Sigrity/Clarity
Strong understanding of transmission line theory, S-parameters, crosstalk, loss mechanisms and channel compliance metrics such as eye diagrams and COM
Experience with IBIS and IBIS-AMI models for SerDes and memory interface simulation
Solid knowledge of PDN design, including impedance targeting, decoupling optimisation and DC IR drop analysis
Hands-on measurement with VNAs, TDRs and high-speed oscilloscopes
Ability to correlate measurements with simulation
Experience with 56G/112G PAM4 channels or PCIe Gen5/6 compliance
Package and interposer co-simulation, including chip-package-board analysis
Knowledge of low-loss PCB materials and fabrication tolerances and their effect on high-speed performance
Scripting with Python or MATLAB to automate simulation and post-processing

Benefits

Comp & perks

Equal opportunity employer
Hiring decisions based on skills, experience and potential
Support and adjustments during the hiring process
Opportunity to work on optical computing for AI and sustainable intelligence at global scale
Opportunity to contribute to products moving from first product to volume production
Cross-disciplinary collaboration with optical engineers, machine learning researchers, and hardware and software engineers
Opportunity to have a real say in how the product, team and ways of working are built