Digital IC Design Intern, MS

Marvell Technology

. Deep dive into the digital design and implementation of real chip design efforts .

Posted 9/21/2026internshipUnited StatesEntry Level💰 $35 - $70 per hourWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in RTL design and verification, with a strong foundation in digital design principles and methodologies. Proficient in using industry-standard tools for synthesis, timing analysis, and debugging within the ASIC design flow.

Highest-signal resume keywords

RTL DesignStatic Timing AnalysisVerilogPython ProgrammingSynopsys Tools

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Digital DesignCircuit DesignDigital Logic DesignVLSISoC DesignASIC DesignPower AnalysisDebuggingTiming SignoffDigital Signal Processing

Soft Skills

Problem SolvingCommunication

Tools & Technologies

Synopsys PrimetimeCadence VirtuosoCadence Spectre XMentor Tools

Industry Keywords

High-Speed Connectivity DevicesChip DesignEmerging MethodologiesDesign QualityDesign Efficiency

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Deep dive into the digital design and implementation of real chip design efforts
Develop and verify detailed, high-performance RTL design blocks
Apply digital design specifications for high-speed connectivity devices and next-generation chips
Conduct synthesis, static timing analysis, timing signoff, and power analysis
Debug design issues and ensure functional correctness
Investigate and execute new design techniques and flows
Explore emerging methodologies to improve design quality, efficiency, and productivity
Collaborate with chip architecture, design verification, and physical design teams to solve complex problems
Contribute to a team building real products

Requirements

What you’ll need

Currently enrolled in a Master’s Degree in Electrical Engineering, Computer Engineering, or a related field
Expected graduation date between Fall 2027 – Summer 2028
Completed courses focusing on circuit design, circuit theory, digital logic design, static timing analysis, computer architecture, Verilog, VLSI, digital signal processing (DSP), SoC/ASIC design, or electronics
Proficiency in programming and scripting languages such as Python, Perl, and Tcl
Experience using Synopsys (Primetime), Cadence (Virtuoso and Spectre X), and Mentor tools
Hands-on experience with RTL design and a firm understanding of its integration into the overall ASIC design flow
Strong analysis, problem solving, and communication skills
Must be eligible to access export-controlled information under applicable U.S. law; applicants may be subject to an export license review process

Benefits

Comp & perks

Medical, dental, and vision coverage
Perks and discounts
Robust mental health resources
Paid holidays
Additional compensation may be available for intern PhD candidates