Marvell Technology

Accounting Manager

• Assist with preparation of global journal entries, account reconciliations, financial analyses, SEC filing schedules, 10-Q and earnings press release tie-outs, and SOX controls documentation
• Support monthly general ledger close and consolidation processes using Oracle ERP
• Participate in ad-hoc accounting projects, including process improvements and automation initiatives
• Work with SEC Financial Reporting, Technical Accounting, Global GL Consolidations, and Global Accounting Policy teams
• Gain exposure to GAAP, SEC reporting, and corporate financial practices

Accounting Intern

Application Engineer

• Serve as the primary hardware technical focal for strategic accounts
• Drive design-in activities from schematic review through board bring-up, EDVT, and mass production
• Review customer PCB schematics and layout files for Marvell DC switch platforms
• Provide guidance on component selection, power sequencing, clock distribution, and high-speed signal routing
• Perform or coordinate SI/PI simulations for high-speed Ethernet interfaces at 800G, 1.6T, and beyond
• Evaluate channel performance, SerDes tuning, and PAM4 link margin
• Support hardware bring-up at customer sites and in Marvell's Taipei lab
• Debug SerDes link training, power integrity, thermal, and interface failures
• Author and review hardware design guides, application notes, schematic checklists, and layout guidelines
• Participate in EE/ME/SI/PI design reviews with Marvell's global hardware engineering team
• Represent customer requirements and provide design insights to silicon and platform teams
• Develop knowledge of UALink, ESUN, CPO, and 224G SerDes
• Contribute to internal training and knowledge-sharing forums
• Engage Taiwan's supply chain ecosystem to optimize platform designs
• Work closely with customers' hardware teams, Marvell's global engineering organization, and cross-functional SI/PI, PSE, and software AE teams

Principal Hardware Application Engineer

Compliance

• Provide strategic leadership, oversight, and day-to-day management of the IT SOX compliance program
• Oversee IT risk assessment and scoping aligned with financial reporting risks
• Review control documentation and collaborate with control owners to ensure adequate process execution and documentation
• Coordinate ITGC and ITAC control testing with internal audit, external audit, and control owners
• Support new systems implementations and technology changes to incorporate SOX requirements
• Train and guide IT control owners on SOX expectations, documentation standards, and audit readiness
• Improve the SOX program through automation, metrics, tools, and process improvements
• Collaborate with Internal Audit, IT, and business leaders to remediate control deficiencies on time

Senior IT SOX/Compliance Manager

Program Manager

• Manage IP development and delivery to Marvell product business units
• Develop plans to deliver and support SoC IP from conception through program Mass Production Release (MPR)
• Drive closure of IP specifications and requirements
• Chair weekly cross-functional meetings assessing status, milestones, and plan completeness
• Provide regular program updates to Marvell executive stakeholders
• Support Marvell’s Program Management Process
• Provide matrixed leadership of engineering program managers across the engineering organization
• Execute lessons learned and risk management
• Enforce agreed processes
• Ensure successful IP development and delivery outcomes

Sr. Principal Engineering IP Program Manager

Designer

• Work on physical design and methodology for next-generation, high-performance processor chips
• Work with local and global team members on physical design of complex chips and design methodology
• Collaborate with Digital, RTL, and Analog design teams to ensure timely design convergence and integration
• Implement and support multi-voltage designs through place and route, static timing, and physical verification using industry-standard EDA tools
• Integrate new AI-based design flows
• Work with various teams to drive successful design closure
• Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary
• Write Shell, Python, and TCL scripts to improve productivity through AI and automation

Physical Design CAD Engineer

Solutions Engineer

• Define test strategies and DFT requirements for advanced HSIO technologies
• Influence product testability, observability, and diagnostics during architecture and design phases
• Drive test planning and validation for next-generation SerDes, chiplet, and die-to-die architectures
• Define and execute validation strategies for test chips and first-silicon bring-up
• Characterize IP and subsystem functionality across voltage, frequency, and temperature conditions
• Correlate validation results with manufacturing test requirements
• Develop production screening methodologies and manufacturing test plans
• Collaborate with Product Engineering and Test Engineering teams to enable production deployment
• Analyze production data and drive improvements in quality, yield, and test efficiency
• Partner with Architecture, Design, DFT, Validation, Product Engineering, Reliability, and Manufacturing teams
• Lead cross-functional reviews and influence key technical decisions
• Mentor engineers and contribute to next-generation test methodologies and best practices

HSIO Test Solutions Engineering Lead

SDET

• Test features on Marvell semiconductor chips for internal and external customers
• Ensure underperforming units are not shipped
• Work with design teams to ensure chip features are testable and results meet customer specifications
• Write new code or develop testing strategies when current equipment capabilities are insufficient
• Verify code and test programs across large numbers of individual parts
• Flag parts with unexpected results for further investigation
• Replicate work in the test bench environment
• Conduct correlation exercises with design and verification teams to determine root causes
• Contribute to new product introduction activities, including silicon bring-up and release of sampling, qualification, characterization, and production test programs
• Optimize test time and yield
• Collaborate with design, marketing, program management, quality assurance, and operations teams

Test Engineering Intern

• Test features on Marvell semiconductor chips for internal and external customers
• Verify code and test programs across large numbers of individual parts
• Flag parts producing unexpected results for further investigation
• Replicate work in the test bench environment
• Perform correlation exercises with design and verification teams to determine root causes
• Develop code and new testing strategies when current testing equipment is insufficient
• Support new product introduction activities, including silicon bring-up and release of sampling, qualification, characterization, and production test programs
• Optimize test time and yield
• Collaborate with design, marketing, program management, quality assurance, and operations teams
• Work under the direction of a mentor and team lead

Test Engineering Intern, BS

• Deep dive into the digital design and implementation of real chip design efforts
• Develop and verify detailed, high-performance RTL design blocks
• Apply digital design specifications for high-speed connectivity devices and next-generation chips
• Conduct synthesis, static timing analysis, timing signoff, and power analysis
• Debug design issues and ensure functional correctness
• Investigate and execute new design techniques and flows
• Explore emerging methodologies to improve design quality, efficiency, and productivity
• Collaborate with chip architecture, design verification, and physical design teams to solve complex problems
• Contribute to a team building real products

Digital IC Design Intern, MS

• Deep dive into digital design and implementation of real chip design efforts
• Develop and verify detailed, high-performance RTL design blocks
• Apply digital design specifications for high-speed connectivity devices and next-generation chips
• Conduct synthesis, static timing analysis, timing signoff, and power analysis
• Debug design issues and ensure functional correctness
• Investigate and execute new design techniques and flows
• Explore emerging methodologies to improve design quality, efficiency, and productivity
• Collaborate with chip architecture, design verification, and physical design teams
• Solve complex problems and contribute to building real products

Digital IC Design Intern, BS

Digital IC Design Intern

• Work on real digital chip design and implementation efforts
• Develop and verify high-performance RTL design blocks
• Apply digital design specifications for high-speed connectivity devices and next-generation chips
• Conduct synthesis, static timing analysis, timing signoff, and power analysis
• Debug design issues and ensure functional correctness
• Investigate and execute new design techniques and flows
• Explore emerging methodologies to improve design quality, efficiency, and productivity
• Collaborate with chip architecture, design verification, and physical design teams
• Solve complex problems and contribute to products enabling data infrastructure

Mechanical Engineer

• Collaborate with systems and architecture teams to define SoC-level specifications
• Translate product and protocol requirements into micro-architecture specifications for complex subsystems, high-speed datapaths, DSP pipelines, and IP blocks
• Own RTL development using synthesizable SystemVerilog
• Drive the ASIC front-end design flow, including lint, CDC/RDC, synthesis, timing constraint development, and design-for-test readiness
• Partner with STA and PNR teams on timing closure, floorplanning, congestion analysis, and design optimization
• Lead digital logic integration into subsystems and top-level assemblies
• Develop parameterized datapaths, DSP building blocks, and reusable infrastructure logic
• Work with DV teams on verification strategies, test plans, coverage-driven validation, and power-aware validation
• Support pre-silicon validation through emulation, FPGA prototyping, and performance modeling
• Drive post-silicon bring-up and debug with lab and systems teams
• Participate in design and micro-architecture reviews and improve design, verification, and methodology flows

Senior Staff Digital Design Engineer

Technical Program Manager

• Lead custom and semi-custom semiconductor solutions for customers
• Own the complete program lifecycle from initiation and planning through execution and closure
• Drive execution across development, validation, qualification, sample delivery, and production release phases
• Monitor and control program performance against schedule, quality, and cost targets in the Plan of Record
• Collaborate with engineering, operations, and business teams in a matrixed organization
• Serve as the primary internal and external communications contact at engineering, management, and executive levels
• Identify risks and lead mitigation planning
• Escalate and resolve issues to maintain program momentum
• Lead post-mortems to identify improvement areas and pre-mortems to apply learnings from other programs

Engineering Program Manager

• Work as part of the CnM team on CnM IPs for Switching projects
• Contribute to design and verification of cutting-edge IP development
• Participate in next-generation CnM development
• Collaborate with system, architecture, design, verification, and software engineers
• Implement and perform verification of different design IPs and multidisciplinary systems combining hardware, firmware, and software
• Write test documents
• Define testing processes
• Validate system requirements

Accounting Intern

Principal Hardware Application Engineer

Senior IT SOX/Compliance Manager

Sr. Principal Engineering IP Program Manager

Physical Design CAD Engineer

HSIO Test Solutions Engineering Lead

Test Engineering Intern

Test Engineering Intern, BS

Digital IC Design Intern, MS

Digital IC Design Intern, BS

Digital IC Design Intern

Digital IC Design Intern, MS

Senior Staff Digital Design Engineer

Engineering Program Manager

Design Verification Intern