HSIO Test Solutions Engineering Lead

Marvell Technology

. Define test strategies and DFT requirements for advanced HSIO technologies .

Posted 9/23/2026full-timeIrvine • California • United StatesSenior💰 $138,400 - $204,800 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in semiconductor Test Engineering, including test strategy definition, validation methodologies, and production test development. Proficient in high-speed SerDes technologies and capable of leading cross-functional technical initiatives to enhance product testability and yield.

Highest-signal resume keywords

Semiconductor Test EngineeringHigh-Speed SerDes TechnologiesValidation MethodologiesProduction Test DevelopmentCross-Functional Leadership

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Test Strategy DefinitionSilicon ValidationYield AnalysisDFTMixed-Signal CharacterizationPythonAutomationAnalyticsTest Infrastructure DevelopmentProduction Screening Methodologies

Soft Skills

MentoringCollaborationInfluencing Technical Decisions

Tools & Technologies

Advantest 93KTeradyne UltraFLEXChipletsHeterogeneous Integration Technologies

Industry Keywords

Semiconductor ManufacturingQualification MethodologiesAINetworkingCloudData Center Products

Tech Stack

Tools & technologies

CloudPython

About the role

Key responsibilities & impact

Define test strategies and DFT requirements for advanced HSIO technologies
Influence product testability, observability, and diagnostics during architecture and design phases
Drive test planning and validation for next-generation SerDes, chiplet, and die-to-die architectures
Define and execute validation strategies for test chips and first-silicon bring-up
Characterize IP and subsystem functionality across voltage, frequency, and temperature conditions
Correlate validation results with manufacturing test requirements
Develop production screening methodologies and manufacturing test plans
Collaborate with Product Engineering and Test Engineering teams to enable production deployment
Analyze production data and drive improvements in quality, yield, and test efficiency
Partner with Architecture, Design, DFT, Validation, Product Engineering, Reliability, and Manufacturing teams
Lead cross-functional reviews and influence key technical decisions
Mentor engineers and contribute to next-generation test methodologies and best practices

Requirements

What you’ll need

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, Physics, or related field
10+ years of experience in semiconductor Test Engineering, Product Engineering, DFT, Silicon Validation, or related disciplines
Strong understanding of semiconductor manufacturing, yield analysis, and qualification methodologies
Demonstrated ability to lead complex cross-functional technical initiatives
Experience with high-speed SerDes technologies (56G, 112G, 224G and beyond), PCIe, CXL, UCIe, die-to-die interfaces, DFT, silicon validation and debug, ATE, production test development, or mixed-signal characterization and correlation
Preferred: MS or PhD in Electrical Engineering, Computer Engineering, or related field
Experience with Advantest 93K and/or Teradyne UltraFLEX platforms
Experience with advanced packaging, chiplets, and heterogeneous integration technologies
Experience supporting AI, networking, cloud, or data center products
Python, automation, analytics, or test infrastructure development experience
Must be eligible to access export-controlled information under applicable U.S. law; applicants may be subject to export license review

Benefits

Comp & perks

Bonus and equity plans
New hire equity grant
Annual equity refreshers
Employee stock purchase plan with a 2-year look back
Family support programs
Mental health resources
Recognition and service awards