Senior Staff Digital Design Engineer

Marvell Technology

. Collaborate with systems and architecture teams to define SoC-level specifications .

Posted 9/17/2026full-timeIrvine • California • United StatesSenior💰 $135,900 - $201,130 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in digital ASIC design, including RTL development, micro-architecture specifications, and high-performance DSP implementations. Proficient in collaborating across teams to optimize design flows and ensure successful integration of complex logic blocks.

Highest-signal resume keywords

Digital ASIC DesignRTL DevelopmentHigh-Performance DSP DesignFront-End Design FlowsDebug Skills

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SystemVerilogMicro-Architecture DevelopmentDSP Algorithm ImplementationTiming ClosureSynthesisDesign-For-Test ReadinessParameterization of DatapathsVerification StrategiesPower/Performance OptimizationFEC Architectures

Soft Skills

Excellent CommunicationLeadership SkillsMentoring

Tools & Technologies

LintCDC/RDCSTAFPGA PrototypingEmulation

Industry Keywords

Networking StandardsEthernet ProtocolsHigh-Bandwidth Compute ArchitecturesExport-Controlled InformationAdvanced Process Nodes

About the role

Key responsibilities & impact

Collaborate with systems and architecture teams to define SoC-level specifications
Translate product and protocol requirements into micro-architecture specifications for complex subsystems, high-speed datapaths, DSP pipelines, and IP blocks
Own RTL development using synthesizable SystemVerilog
Drive the ASIC front-end design flow, including lint, CDC/RDC, synthesis, timing constraint development, and design-for-test readiness
Partner with STA and PNR teams on timing closure, floorplanning, congestion analysis, and design optimization
Lead digital logic integration into subsystems and top-level assemblies
Develop parameterized datapaths, DSP building blocks, and reusable infrastructure logic
Work with DV teams on verification strategies, test plans, coverage-driven validation, and power-aware validation
Support pre-silicon validation through emulation, FPGA prototyping, and performance modeling
Drive post-silicon bring-up and debug with lab and systems teams
Participate in design and micro-architecture reviews and improve design, verification, and methodology flows

Requirements

What you’ll need

Extensive experience in digital ASIC design, including micro-architecture development, RTL implementation, and integration of complex logic blocks
3-10+ years of industry experience working on large-scale ASICs for networking, data-center connectivity, or high-bandwidth compute architectures
5-10+ years with a Bachelor's degree, or 3-5+ years with a Master's or PhD
Strong background in high-performance DSP and high-speed datapath design
Familiarity with Ethernet protocols and networking standards, including MAC, PCS framing, flow control, and packet-level behaviors
Proficiency with front-end design flows, including lint, CDC/RDC, synthesis, STA, and power/performance optimization
Ability to collaborate across architecture, verification, physical design, firmware, and systems teams
Strong debug skills across RTL simulation, emulation, FPGA prototypes, and silicon bring-up
Familiarity with advanced process nodes such as 5nm and 3nm
Excellent communication and leadership skills, including mentoring junior engineers and influencing technical direction
BS/MS in Electrical Engineering, Computer Engineering, or related field; PhD is a plus
Advanced high-speed DSP algorithm implementation, including adaptive equalization, channel estimation, and high-throughput filtering architectures
Experience with FEC architectures such as LDPC, RS, or BCH
Previous PHY design experience, including PMA-level DSP pipelines, equalization blocks, clock recovery, and SerDes-adjacent logic
Eligibility to access export-controlled information under U.S. law; some applicants may require export license review

Benefits

Comp & perks

Bonus and equity plans
New hire equity grant
Annual equity refreshers
Employee stock purchase plan with a 2-year look back
Family support programs
Mental health resources
Recognition and service awards