Director, ASIC Physical Design

Nokia

. Define and execute the physical design roadmap, strategy, and technical direction for multiple ASIC projects .

Posted 9/29/2026full-timeSan Jose • California • United StatesLead💰 $179,000 - $256,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in ASIC physical design methodologies and flows, with a strong focus on leadership and team development across global sites. Proven ability to drive advanced design strategies and optimize performance for cutting-edge technology nodes.

Highest-signal resume keywords

ASIC Physical Design FlowLeadership in Multi-Site TeamsLow-Power Design TechniquesEDA Tools ProficiencyCustomer Owned Tooling (CoT) Implementation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

FloorplanningPower Grid DesignPlacementCTSRoutingTiming ClosurePower IntegrityPhysical VerificationDFM/DFYChip-Level IR Analysis

Soft Skills

Exceptional LeadershipCommunication SkillsInterpersonal SkillsInfluencing SkillsTeam Development

Tools & Technologies

Synopsys EDA ToolsCadence EDA ToolsSiemens EDA ToolsAI for Physical Design Flow

Certifications & Qualifications

Master's Degree in Electrical EngineeringMaster's Degree in Computer Engineering

Industry Keywords

ASIC ProjectsGDSII ReleaseAdvanced Technology NodesGlobal Team ManagementTechnical Risk Mitigation

About the role

Key responsibilities & impact

Define and execute the physical design roadmap, strategy, and technical direction for multiple ASIC projects
Lead and manage distributed physical design engineers across the USA, India, and Italy
Mentor, grow, and build a high-performing global team
Drive training and adoption of advanced methodologies, including Customer Owned Tooling flow for robust GDSII release
Develop, adopt, and continuously improve physical design methodologies, flows, and best practices
Oversee floorplanning, power grid design, placement, CTS, routing, timing closure, power integrity, physical verification, and DFM/DFY
Optimize physical design activities for aggressive performance, ultra-low-power, and area targets
Collaborate with architecture, RTL design, DFT, CAD, package, and test teams for seamless integration and first-pass silicon
Manage EDA tool vendor and IP provider relationships
Identify technical risks and develop mitigation strategies
Manage departmental budgets, resources, and project schedules across global sites

Requirements

What you’ll need

Master's degree in Electrical Engineering, Computer Engineering, or a related field
15+ years of progressive experience in ASIC physical design
At least 8 years in a leadership or management role overseeing large, multi-site teams
Deep expertise in ASIC physical design flow, including floorplanning, power planning, placement, CTS, routing, timing closure, power analysis, and physical verification
Proven track record leading multiple complex ASIC tape-outs on advanced/latest technology nodes, including 7nm, 5nm, 3nm and beyond
Significant experience implementing and optimizing low-power design techniques
Experience introducing and deploying new physical design methodologies, including Customer Owned Tooling (CoT) flow leading to successful GDSII release
Strong command of EDA tools from Synopsys, Cadence, and Siemens EDA
Understanding of AI for Physical Design flow development and automation
Understanding of chip-level IR analysis with package models
Exceptional leadership, communication, and interpersonal skills
Ability to influence and drive results across diverse, geographically dispersed teams
Demonstrated ability to attract, develop, and retain engineering talent globally

Benefits

Comp & perks

Laptop support with ordering
Hybrid work arrangement