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Core Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates extensive experience in developing System Verilog UVM-based test environments and executing verification plans for high-complexity DWDM systems. Proficient in managing verification projects with a focus on quality, timeline goals, and collaboration across global teams.
Highest-signal resume keywords
System Verilog UVM-Based Test EnvironmentsHVL Coding SkillsIndustry-Standard Simulators (VCS, NC, MTI)Waveform-Based Debugging ToolsTelecom Protocols Knowledge
ATS Keywords
Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
System VerilogUVMFPGA Functionality ValidationCoverage AnalysisTest Plans DevelopmentHDL (Verilog)Scripting Languages (Perl)RTL DesignDWDM SystemsTest Scenarios Creation
Soft Skills
Analytical SkillsTroubleshooting SkillsWritten CommunicationOral CommunicationLeadership Capability
Tools & Technologies
VCSNCMTIWaveform Debugging ToolsEthernetPCIeI2CSPI
Industry Keywords
Telecom ProtocolsVerification MethodologiesOptical Network ApplicationsCross-Functional CollaborationProduct Lifecycle Management
Tech Stack
Tools & technologiesPerl
About the role
Key responsibilities & impact- Develop and execute verification plans for high-complexity DWDM systems used in LH/ULH optical network applications
- Design and implement simulation environments and testbenches to validate FPGA functionality and performance
- Create and run functional and directed/random test scenarios to ensure comprehensive design coverage
- Perform detailed coverage analysis and implement strategies to achieve full functional and code coverage
- Collaborate closely with cross-functional R&D teams across multiple global locations throughout the product lifecycle
- Provide lab support during board bring-up and assist in root cause analysis to ensure first-time-right product quality
- Independently manage verification projects with a proactive and solution-driven approach to meet quality and timeline goals
Requirements
What you’ll need- Must have 12–16 years of experience in developing System Verilog UVM-based test environments and developing and implementing test plans at block, sub-chip, and chip levels
- Must have strong HVL coding skills for verification
- Hands-on experience with industry-standard simulators such as VCS, NC, and MTI
- Experience with waveform-based debugging tools
- Exposure to UVM or similar verification methodologies is required
- Familiarity with HDLs such as Verilog
- Familiarity with scripting languages such as Perl is highly desired
- Working knowledge of RTL design is preferred
- Conversant with Ethernet, PCIe, I2C, and SPI technologies
- Knowledge of telecom protocols is preferred
- Structured and thorough, with analytical and troubleshooting skills
- Good written and oral communication skills are required
- Flexible, innovative, self-driven, and willing to take initiatives
- Highly motivated team player with exceptional leadership capability
- Bachelor’s degree
Benefits
Comp & perks- Flexible and hybrid working arrangements to support work–life balance
- Health and well-being support – medical insurance for you and your family, health check-ups, life and accident insurance, well-being programs, and employee resource groups
- A minimum of 90 days of Maternity and Paternity Leave based on eligibility
- Personal Support Service 24/7 – a confidential support channel open to all Nokia employees and their families in challenging situations
- Career growth & mobility – technical career paths, job rotations, international assignments, and relocation support
- Continuous learning – technical certifications, mentoring programs, coaching, and digital learning platforms
- Opportunities to innovate and contribute through Nokia’s research and development environment
- Recognition programs that celebrate outstanding contributions
- Workplace support – ergonomic working support and mobile device programs based on eligibility