Principal ASIC Design Engineer

Nokia

. Interpret and map documents from standard bodies to requirements/functions .

Posted 10/12/2026full-timeBangalore • IndiaLeadWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in ASIC design and development, including RTL coding, microarchitecture definition, and low-power design techniques. Proven ability to lead cross-functional teams and mentor engineers while managing the full delivery lifecycle from requirements analysis to silicon qualification.

Highest-signal resume keywords

ASIC Design ActivitiesRTL CodingMicroarchitecture DefinitionEnd-to-End ASIC DevelopmentLow-Power ASIC Design Techniques

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

ASIC DesignRTL CodingMicroarchitecture DefinitionLow-Power Design TechniquesClock Domain CrossingAMS Verification MethodologiesSilicon Bring-UpLab ValidationSynthesisTiming Reports

Soft Skills

Technical LeadershipMentoringCollaboration

Tools & Technologies

EDA ToolsSynopsysCadenceMentor

Industry Keywords

EthernetNetworkingRequirements AnalysisVerificationSilicon Qualification

About the role

Key responsibilities & impact

Interpret and map documents from standard bodies to requirements/functions
Work with architecture and cross-functional teams including SDK, verification, and emulation teams
Comprehend high-level requirements and create microarchitecture documents
Provide technical leadership to a team of designers
Own delivery through planning, definition, and implementation phases
Perform ASIC design activities including RTL coding, lint, CDC, RDC, and synthesis
Review architecture, requirements, microarchitecture, synthesis, and timing reports
Work with verification and lab validation teams to debug and qualify the implementation
Own a major ASIC/function from requirements analysis through implementation, verification, and silicon qualification

Requirements

What you’ll need

Bachelor's degree or higher in Computer Science or Electrical Engineering with very good academics
10+ years of experience and hands-on experience in delivery of a major function/ASIC
Preferred: Prior experience in Ethernet/Networking domain
Ability to mentor and bring together engineers with differing but valid technical viewpoints
Strong experience in end-to-end ASIC development
Experience in microarchitecture definition and RTL design
Experience with low-power ASIC design techniques and clock domain crossing
Knowledge of AMS verification methodologies
Exposure to silicon bring-up and lab validation
Familiarity with EDA tools from Synopsys, Cadence, or Mentor

Benefits

Comp & perks

Laptop support with ordering needed
Hybrid work arrangement