Principal SoC DFT Engineer

Nokia

. Work on DFT architecture and implementation across logic BIST, MBIST, BISR, Boundary Scan, and JTAG .

Posted 10/2/2026full-timeSan Jose • California • United StatesLead💰 $159,783 - $296,739 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive experience in DFT architecture and implementation, including Logic BIST, MBIST, and JTAG, with a strong focus on DFT verification and automation through TCL scripting. Proven ability to collaborate across teams to ensure successful silicon outcomes and resolve complex DFT issues.

Highest-signal resume keywords

DFT Implementation ExperienceLogic BIST Insertion And VerificationTCL Scripting SkillsATPG Pattern GenerationGate-Level Simulation And Debugging

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

DFT ArchitectureLogic BISTMBISTBISRBoundary ScanJTAGDFT VerificationDFT DRC ClosureTiming Constraints DevelopmentDFT Automation

Soft Skills

Attention To DetailSense Of OwnershipVerbal CommunicationWritten Communication

Tools & Technologies

EDA ToolsIndustry Simulator Tools

Industry Keywords

IEEE 1149.xSilicon DebugTest Coverage ImprovementPre-Silicon DFT SignoffPost-Silicon Pattern Bring-Up

About the role

Key responsibilities & impact

Work on DFT architecture and implementation across logic BIST, MBIST, BISR, Boundary Scan, and JTAG
Own end-to-end DFT insertion, verification, DRC closure, and test coverage closure from RTL/netlist through post-silicon debug
Collaborate with architecture, IP design, Physical Design, RTL, and product engineering teams to achieve first-pass silicon success
Perform hands-on Logic BIST, scan compression, MBIST, BISR, Boundary Scan, JTAG, and high-speed analog/mixed-signal IP integration
Execute DFT verification, debug, and DFT DRC closure at block and top levels
Run, analyze, and debug DFT/RTL checks and resolve violations
Generate, simulate, and debug MBIST and logic ATPG patterns
Analyze test results and drive test coverage improvement and closure
Develop and validate DFT timing constraints for scan, BIST, and test modes
Create and maintain TCL scripts for DFT insertion, verification, and analysis automation
Support hierarchical DFT implementation and resolve integration issues
Support pre-silicon DFT signoff and post-silicon pattern bring-up and debug
Assist with ATE pattern conversion and debug
Perform gate-level simulation and debugging with industry simulator tools

Requirements

What you’ll need

Bachelor’s degree in computer science, Electrical Engineering or related fields and 8 years of related professional experience OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5 years of experience
5+ years of hands-on DFT implementation experience
Strong proficiency with EDA tools
Logic BIST insertion and verification
MBIST / BISR insertion and verification
Boundary Scan (IEEE 1149.x)
JTAG and HS Analog/mixed signal IP IOBIST integration
ATPG pattern generation and coverage analysis
Proven ability to resolve DFT DRCs, connectivity issues, and testability problems
Strong TCL scripting skills for DFT automation and flow execution
Experience developing and validating scan and test-mode timing constraints
End-to-end DFT lifecycle experience, from RTL/netlist through silicon debug
Strong debugging skills, attention to detail, and sense of ownership
Excellent verbal and written communication skills
Experience with gate-level simulations and debugging with industry simulator tools

Benefits

Comp & perks

Laptop support with ordering provided