Senior ASIC Design Engineer

Nokia

. Work closely with architects to understand requirements, document them, and implement functional blocks or IP .

Posted 9/21/2026full-timeBangalore • IndiaSeniorWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in RTL coding, uArch design, and timing constraints development, with a strong ability to debug and validate designs. Proficient in using Verilog/SystemVerilog and familiar with ASIC or FPGA tools for synthesis and verification.

Highest-signal resume keywords

RTL Coding Using Verilog/SystemVerilogUArch DesignTiming Constraints DevelopmentSynthesis Using ASIC or FPGA ToolsDebugging and Validation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL CodingUArchTiming Constraints DevelopmentLint ChecksCDC ChecksSynthesisLogic DesignFIFOsState MachinesAssertions

Soft Skills

Ability to Abstract Complex Functions

Tools & Technologies

ASIC ToolsFPGA Tools

Industry Keywords

EthernetNetworking

About the role

Key responsibilities & impact

Work closely with architects to understand requirements, document them, and implement functional blocks or IP
Capture design intent, uArch, RTL coding, API coding, lint, constraints development, CDC, and synthesis
Debug designs and work with verification team members to achieve functionally clean blocks
Integrate blocks and create physical design blocks for place and route
Work with the Physical Design team to ensure area, timing, and power requirements are met
Test design blocks in the lab and work with lab validation team members

Requirements

What you’ll need

Bachelor’s degree
Ability to abstract complex functions
Ability to do the uArch using block diagrams, waveforms and mathematical and logical models/equations
Good understanding of FIFOs and state machines
Exposure to RTL coding using Verilog/SystemVerilog
Good logic design skills with ability to understand timing, area and power reports
Experience in timing constraints development
Experience running lint and CDC checks
Experience with synthesis using ASIC or FPGA tools
Interest in using assertions and formal property verification
5+ years of experience in design, including uArch, RTL coding, RTL checks and debug
Prior experience in Ethernet/Networking domain preferred

Benefits

Comp & perks

Flexible and hybrid working arrangements to support work–life balance
Medical insurance for you and your family
Health check-ups
Life and accident insurance
Well-being programs
Employee resource groups
A minimum of 90 days of Maternity and Paternity Leave based on eligibility
Personal Support Service 24/7 for Nokia employees and their families
Technical career paths
Job rotations
International assignments
Relocation support
Technical certifications
Mentoring programs
Coaching
Digital learning platforms
Opportunities to innovate and contribute through Nokia’s research and development environment
Recognition programs
Ergonomic working support based on eligibility
Mobile device programs based on eligibility