Analog Design Engineer – Custom DRAM Circuits

Normal Computing

. Build the core mixed-signal technology powering Normal Computing's unconventional computing architecture .

Posted 10/16/2026full-timeMountain View • California • United StatesMid-LevelSenior💰 $200,000 - $400,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in analog circuit design and development, including the creation of analog IP and memory technologies such as SRAM and DRAM. Proficient in the Cadence flow and capable of leading end-to-end analog development processes.

Highest-signal resume keywords

Analog Circuit DesignAnalog IP DevelopmentCadence Flow ProficiencyMemory Technology ExpertiseSilicon Bring-Up Experience

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Analog Circuit DesignAnalog IP DevelopmentMemory Technology DesignCustom Bitcell CharacterizationSilicon Bring-UpParasitic ExtractionNoise and Variation AnalysisAI and Scripting LanguagesDebugging and CharacterizationTapeout Experience

Tools & Technologies

Cadence VirtuosoCadence SpectreCadence AssemblerCadence ExtractionCadence LayoutHSMCCharacterization Tools

Industry Keywords

Mixed-Signal TechnologyComputational ArchitectureCIM ChipsBitcell ArraysPeripheral Circuits

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Build the core mixed-signal technology powering Normal Computing's unconventional computing architecture
Design unique analog circuits, including library cells and macros
Support Normal Computing's unique computational architecture
Collaborate with silicon architecture, digital, and layout teams
Own end-to-end analog development from clean-sheet circuit design through parasitic extraction and silicon bring-up
Lead the full analog development cycle, including research and exploratory design
Develop or acquire analog IP for use in Normal Silicon
Acquire or help direct analog EDA tool development
Evaluate memory designs, including SRAM, DRAM, and compute-in-memory architectures

Requirements

What you’ll need

Experience developing analog IP from specification to GDSII in modern technologies, including tapeout and silicon bring-up
Experience with memory technologies such as SRAM and DRAM at the core level, including bitcell arrays and peripheral circuits
Experience designing and characterizing custom bitcells in schematic and layout
Fluency in the Cadence flow: Virtuoso, Spectre, Assembler, Extraction, Layout, HSMC, and Characterization
Deep understanding of noise and variation and their impacts on silicon performance and reliability
Experience leading, taping out, and bringing up CIM chips is a bonus
Experience in chip measurement environments for debugging and characterization is a bonus
Experience using AI and/or scripting languages such as Python or Perl to automate design flows and data post-processing is a bonus

Benefits

Comp & perks

Equity
Competitive and equitable compensation
Inclusive environment
Reasonable accommodations for individuals with disabilities