Normal Computing

Hardware Engineer

• Lead the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis, and place-and-route
• Own static timing analysis, timing constraint creation and validation, and signoff timing closure across operating corners and modes
• Drive physical optimization for power, performance, and area, plus power integrity and crosstalk analysis
• Execute chip/block physical signoff checks, including DRC, LVS, ERC, and antenna fixes, and hand off to the foundry
• Collaborate with RTL, architecture, and DFT teams on floorplanning, macro placement, pin assignments, and physical feasibility
• Create and execute tapeout checklists and manage final stream-out processes
• Support post-silicon physical debugging and bring-up as needed

Hardware Engineer, Physical Design