Hardware Engineer, DFT

Normal Computing

. Own DFT architecture and implementation for next-generation, physics-inspired ASICs from early RTL design through tapeout and silicon bring-up .

Posted 10/22/2026full-timeMountain View • California • United StatesSeniorLeadWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in DFT architecture and implementation for ASICs, including scan insertion, ATPG, and boundary scan strategies. Proven ability to deliver production-ready test patterns and collaborate effectively across cross-functional teams.

Highest-signal resume keywords

DFT Architecture OwnershipScan Insertion ExpertiseATPG Pattern GenerationSiemens Tessent ProficiencyPython Scripting Skills

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

DFT ImplementationScan CompressionFault Coverage AnalysisTest Pattern GenerationMBISTBoundary Scan/JTAGDFT IntegrationStatic Timing AnalysisMemory RedundancyBuilt-In Self-Repair (BISR)

Soft Skills

Effective CommunicationCross-Functional CollaborationIndependent Decision-Making

Tools & Technologies

Siemens TessentSynopsys TestMAXCadence ModusEDA ToolsAI-Assisted Tools

Industry Keywords

ASICSoCIEEE 1500IEEE 1687 (IJTAG)Hierarchical DFTAdvanced Scan CompressionSilicon DiagnosisYield ImprovementSilicon Bring-UpManufacturing Test Patterns

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Own DFT architecture and implementation for next-generation, physics-inspired ASICs from early RTL design through tapeout and silicon bring-up
Define and drive scan/ATPG, MBIST, and boundary-scan strategies
Define chip-level DFT architecture, including scan insertion, ATPG, scan compression, MBIST, boundary scan/JTAG, and test access infrastructure
Drive DFT insertion and integration across RTL, synthesis, and physical design
Own DFT verification, ATPG pattern generation, fault coverage analysis, test-mode validation, and DFT signoff through tapeout
Deliver production-ready test patterns and test collateral to manufacturing partners, including documentation for ATE integration, silicon bring-up, and diagnosis
Establish scalable DFT flows, automation, and best practices using industry-standard EDA tools
Define technical requirements, oversee contracted DFT work, and review external partner deliverables
Collaborate with RTL, verification, physical design, silicon product engineering, manufacturing, and external partners

Requirements

What you’ll need

7+ years of experience in DFT implementation for complex ASICs or SoCs, including successful tapeouts
Strong hands-on expertise in scan insertion, ATPG, scan compression, fault coverage analysis, and test pattern generation
Proven experience with MBIST, boundary scan/JTAG, and DFT integration across RTL and gate-level designs
Proficiency with Siemens Tessent, Synopsys TestMAX, or Cadence Modus
Solid understanding of RTL design, synthesis, static timing analysis, and physical design considerations
Experience delivering manufacturing test patterns and collaborating with silicon product engineering or ATE teams
Strong scripting skills in Python, Tcl, or similar languages
Ability to independently own DFT architecture, drive cross-functional technical decisions, and communicate effectively across design, verification, and product engineering teams
Experience establishing DFT architecture and methodology from the ground up for a new ASIC program
Familiarity with IEEE 1500, IEEE 1687 (IJTAG), hierarchical DFT, and advanced scan compression techniques
Experience with memory redundancy, built-in self-repair (BISR), silicon diagnosis, and yield improvement
Experience working with external DFT implementation partners or managing outsourced DFT deliverables
Exposure to AI accelerators, memory-intensive architectures, or unconventional computing systems
Experience using AI-assisted or agentic tools to automate silicon design and verification workflows

Benefits

Comp & perks

Equal Employment Opportunity Employer
Inclusive environment committed to diversity
Reasonable accommodations for individuals with disabilities