Hardware Engineer, FPGA

Normal Computing

. Lead selection, procurement, and bring-up of FPGA prototyping platforms for pre-silicon RTL validation and software development .

Posted 10/14/2026full-timeUnited StatesMid-LevelSenior💰 $250,000 - $340,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in FPGA design and implementation, particularly in RTL validation, timing closure, and high-speed I/O design. Proficient in using Xilinx tools and languages such as SystemVerilog and Python for automation and debugging.

Highest-signal resume keywords

FPGA Design and ImplementationExpert-Level SystemVerilogXilinx Vivado ProficiencyHigh-Speed I/O DesignPython Automation Skills

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

FPGA DesignRTL ValidationTiming ClosureSystemVerilogXilinx VivadoPCIe ImplementationPython ProgrammingBoard-Level Bring-UpLab DebuggingVerification Frameworks

Soft Skills

Independent Problem SolvingAdaptability

Tools & Technologies

Vivado IP IntegratorLogic AnalyzersOscilloscopesGitLab CIDocker

Industry Keywords

ASIC DesignMulti-Clock-Domain ArchitecturesCDC BridgesDevice CharacterizationAutomated Test EnvironmentsSignal ProcessingMixed-Signal ASICSERDES TuningCI/CD for Hardware

Tech Stack

Tools & technologies

DockerPythonC++

About the role

Key responsibilities & impact

Lead selection, procurement, and bring-up of FPGA prototyping platforms for pre-silicon RTL validation and software development
Adapt and implement complex ASIC RTL on FPGA targets, including multi-clock-domain architectures, CDC bridges, and timing closure on dense designs
Integrate in-house designs with third-party and vendor IP
Serve as the expert on the AMD/Xilinx ecosystem, including Vivado IP Integrator, transceivers, and memory controllers
Design, implement, and validate high-speed I/O, especially PCIe for accelerator cards in standard servers
Build FPGA-based tester designs for silicon bring-up, device characterization, and automated test environments
Develop Python/C++ hardware-abstraction software, register-map generation, and automated build and regression flows
Root-cause timing and functional issues in the lab using ILA/Vivado Analyzer, oscilloscopes, logic analyzers, and BER/eye-diagram characterization
Work daily with silicon, EDA, and research teams across the FPGA lifecycle

Requirements

What you’ll need

Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware
Expert-level SystemVerilog and/or VHDL for synthesis
Deep proficiency in Xilinx Vivado, including synthesis, place & route, timing closure, and IP catalog
Hands-on experience implementing and debugging PCIe, AXI/AHB, SPI, UART, JTAG, and other common interfaces
Strong Python for automation, test, and build tooling
Strong board-level bring-up and lab debugging skills on real hardware
Ability to work independently, pivot quickly, and address ambiguous problems spanning hardware, software, and physics
Experience with verification frameworks such as Cocotb or UVM is a bonus
Experience deploying ML models to FPGAs or building real-time, sub-microsecond signal-processing pipelines is a bonus
Mixed-signal ASIC exposure is a bonus
SERDES tuning and signal-integrity fundamentals are a bonus
CI/CD for hardware using GitLab CI and Docker-based build and test is a bonus

Benefits

Comp & perks

Equity
Equal opportunity employer committed to diversity and inclusion
Reasonable disability accommodations