Hardware Engineer, Physical Design

Normal Computing

. Lead the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis, and place-and-route .

Posted 9/30/2026full-timeMountain View • California • United StatesMid-LevelSenior💰 $200,000 - $400,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in leading the physical design flow from netlist to GDSII, including static timing analysis, physical optimization, and signoff processes. Proficient in collaborating with cross-functional teams to ensure successful tapeouts and physical feasibility.

Highest-signal resume keywords

Physical Design Flow LeadershipStatic Timing AnalysisPhysical Design Tools ProficiencyTapeout ManagementCollaboration with RTL and DFT Teams

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

FloorplanningPower Grid DesignPlacementClock Tree SynthesisPlace-and-RouteTiming Constraint CreationTiming ClosurePower Integrity AnalysisCrosstalk AnalysisDRC/LVS/ERC Checks

Soft Skills

Problem-SolvingCollaboration

Tools & Technologies

InnovusIC Compiler IITempusPrimeTimePegasusCalibreTCLPython

Industry Keywords

TapeoutsAdvanced Technology NodesHigh-Performance ComputingCustom Memory/Macro FloorplanningHierarchical Top-Level ImplementationAdvanced Packaging

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Lead the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis, and place-and-route
Own static timing analysis, timing constraint creation and validation, and signoff timing closure across operating corners and modes
Drive physical optimization for power, performance, and area, plus power integrity and crosstalk analysis
Execute chip/block physical signoff checks, including DRC, LVS, ERC, and antenna fixes, and hand off to the foundry
Collaborate with RTL, architecture, and DFT teams on floorplanning, macro placement, pin assignments, and physical feasibility
Create and execute tapeout checklists and manage final stream-out processes
Support post-silicon physical debugging and bring-up as needed

Requirements

What you’ll need

At least 3+ successful tapeouts from netlist to signoff, ideally across advanced technology nodes
Deep hands-on experience with industry-standard physical design tools, including Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, and Calibre
Experience across floorplanning, place-and-route (P&R), clock tree synthesis (CTS), and signoff timing closure
Strong problem-solving skills analyzing and resolving STA timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violations
Ability to collaborate with RTL, architecture, and DFT teams on floorplanning, pin placement, and early physical feasibility
Experience at an AI or high-performance computing chip startup (bonus)
Experience with custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging (bonus)
Hands-on experience developing or maintaining automated TCL/Python scripting frameworks for physical design flows (bonus)

Benefits

Comp & perks

Equity
Competitive and equitable compensation
Reasonable accommodations for individuals with disabilities